9baa57158d
intel/genxml: update PIPE_CONTROL so that we can decode it on the CCS
...
Signed-off-by: Rohan Garg <rohan.garg@intel.com >
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28013 >
2024-03-06 14:37:11 +00:00
19aeb274e6
genxml: generate opencl temporary variables with private qualifier
...
To avoid generic pointers, makes the NIR prints a bit more readable.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Acked-by: Caio Oliveira <caio.oliveira@intel.com >
Fixes: 41b2ed65https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27637 >
2024-02-20 14:41:43 +00:00
76c3d97c84
intel/shaders: add iris variant of indirect draws generation shader
...
Iris does not use Gfx11+ SGVS extended parameters, so we have to rely
on the old Gfx9 method of providing the parameters through vertex
buffers.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26797 >
2024-02-13 00:06:45 +00:00
b52e25d3a8
anv: rewrite internal shaders using OpenCL
...
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26797 >
2024-02-13 00:06:45 +00:00
472f49ef43
genxml: remove NDEBUG_UNUSED
...
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26797 >
2024-02-13 00:06:45 +00:00
41b2ed65e2
genxml: generate opencl packing headers
...
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26797 >
2024-02-13 00:06:45 +00:00
2a0328ba8b
genxml: enable opencl code generation
...
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26797 >
2024-02-13 00:06:45 +00:00
df0fe0dfbd
intel/genxml/xe2: Remove L3ALLOC
...
This register don't exist in Xe2 and there is no Bspec page with
another register to be programmed with L3 allocation layout so
intel_get_l3_config() can also always return NULL for Xe2.
Still allowing intel_get_l3_config() to return non-null because
intel_l3_config is used to calculate TBIMR parameters, see
intel_calculate_tile_dimensions().
Signed-off-by: José Roberto de Souza <jose.souza@intel.com >
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26742 >
2024-01-18 14:16:17 +00:00
78a881af43
intel/genxml: add GAM done register description
...
Useful if you encounter some kind of pagefault (including with
AUX-TT).
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Reviewed-by: Tapani Pälli <tapani.palli@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27058 >
2024-01-15 11:16:40 +00:00
547c2f3d3f
intel/genxml: add CCS_INSTDONE register
...
Gives us the ability to check whether the compute command streamer is
hung.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Reviewed-by: Tapani Pälli <tapani.palli@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27058 >
2024-01-15 11:16:40 +00:00
e9b633619c
intel/genxml: Add RENDER_SURFACE_STATE for xe2
...
The indirect BO of clear color is also removed along with clear value
address and its enabling.
Other delta in struct RENDER_SURFACE_STATE are deferred to their
functional enabling changes.
Signed-off-by: Zhang, Jianxun <jianxun.zhang@intel.com >
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com >
Signed-off-by: Rohan Garg <rohan.garg@intel.com >
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26801 >
2024-01-02 21:14:42 +00:00
db5be18862
intel/genxml/gfx125: Move STATE_SURFACE_TYPE to enum
...
This will allow us to use it in Xe2 genxml.
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com >
Signed-off-by: José Roberto de Souza <jose.souza@intel.com >
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26801 >
2024-01-02 21:14:42 +00:00
772ce98a81
intel/genxml/gfx125: Move L1_CACHE_CONTROL to enum
...
This will allow us to use it in Xe2 genxml.
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com >
Signed-off-by: José Roberto de Souza <jose.souza@intel.com >
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26801 >
2024-01-02 21:14:42 +00:00
b741a9a851
anv: Set PIPELINE_SELECT systolic mode enable flag
...
Set the flag on compute shaders when the application has enabled the
cooperative matrix feature. We might still want to enable this only when
DPAS is actually used. The current method is based on many suggestions
from Lionel.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25994 >
2023-12-29 20:28:54 -08:00
4868408e6e
intel/genxml: Add 3DSTATE_PS definitions needed for dual-SIMD8 dispatch on Gfx12+.
...
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26585 >
2023-12-22 18:05:31 +00:00
30faa7a483
anv, iris, intel/genxml: Update 3DSTATE_HS for xe2
...
Update 3DSTATE_HS programming for xe2
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com >
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26600 >
2023-12-18 15:41:31 +00:00
8ba9988858
anv, iris, intel/genxml: Update 3DSTATE_GS for xe2
...
Update 3DSTATE_GS programming for xe2
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com >
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26600 >
2023-12-18 15:41:31 +00:00
a659b1f0c0
anv, blorp, iris, intel/genxml: Update 3DSTATE_PS_EXTRA for xe2
...
Update 3DSTATE_PS_EXTRA programming for xe2
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com >
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26600 >
2023-12-18 15:41:31 +00:00
5548e6a478
anv, blorp, iris, intel/genxml: Update 3DSTATE_VS for xe2
...
Update 3DSTATE_VS programming for xe2
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com >
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26600 >
2023-12-18 15:41:31 +00:00
f170995e66
anv, blorp, iris: Update 3DSTATE_PS programming for xe2
...
Rework:
* Jordan: Move code into intel_update_ps_state()
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com >
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26600 >
2023-12-18 15:41:30 +00:00
80d9294d2d
intel/isl: update 3DSTATE_STENCIL_BUFFER (xe2)
...
Update xml file and adjust driver code to compile.
Signed-off-by: Zhang, Jianxun <jianxun.zhang@intel.com >
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26600 >
2023-12-18 15:41:30 +00:00
2a49a598ce
intel/genxml: update 3DSTATE_DEPTH_BUFFER instruction (xe2)
...
Signed-off-by: Zhang, Jianxun <jianxun.zhang@intel.com >
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26600 >
2023-12-18 15:41:30 +00:00
99eadc2ecb
intel/genxml: Add UNIFIED_COMPRESSION_FORMAT enum for xe2
...
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com >
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26600 >
2023-12-18 15:41:30 +00:00
2c41811808
intel/genxml: update 3DSTATE_WM_HZ_OP instruction (xe2)
...
The depth clear value is provided from 3DSTATE_WM_HZ_OP now.
Signed-off-by: Zhang, Jianxun <jianxun.zhang@intel.com >
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26600 >
2023-12-18 15:41:30 +00:00
5d4a995294
intel/genxml: Remove 3DSTATE_CLEAR_PARAMS instruction (xe2)
...
Signed-off-by: Zhang, Jianxun <jianxun.zhang@intel.com >
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26600 >
2023-12-18 15:41:30 +00:00
2aea09c8de
intel/genxml: Add BCS/VD0 aux table base address register
...
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com >
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26409 >
2023-12-14 00:53:15 +00:00
6d42333b16
intel/genxml/xe2: Update PIPELINE_SELECT
...
'Media Sampler DOP Clock Gate Enable' and 'Force Media Awake' don't
exist anymore.
Signed-off-by: José Roberto de Souza <jose.souza@intel.com >
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26403 >
2023-12-07 14:16:18 +00:00
9898c719a2
intel/genxml/xe2: Update PIPE_CONTROL
...
'Tile Cache Flush Enable' and 'Generic Media State Clear' are now
reserved bits in gfx20+.
Signed-off-by: José Roberto de Souza <jose.souza@intel.com >
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26403 >
2023-12-07 14:16:18 +00:00
36480b4d02
intel: Generate source file with utf-8 encoding from mako template
...
Make them generated in consistent way
Signed-off-by: Yonggang Luo <luoyonggang@gmail.com >
Acked-by: Eric Engestrom <eric@igalia.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26515 >
2023-12-07 12:41:07 +00:00
05632fc9eb
intel/genxml: Update 3DSTATE_TE for xe2
...
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com >
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26438 >
2023-12-02 02:22:07 +00:00
a499be0ee3
intel/genxml: Update IDD for new fields
...
Signed-off-by: Rohan Garg <rohan.garg@intel.com >
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26390 >
2023-12-01 02:36:12 +00:00
c916038b89
intel/genxml: Update COMPUTE_WALKER_BODY for xe2
...
Reworks:
* Caio: Change patch to only add COMPUTE_WALKER_BODY and
EXECUTE_INDIRECT_DISPATCH (that uses it).
Signed-off-by: Rohan Garg <rohan.garg@intel.com >
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26390 >
2023-12-01 02:36:12 +00:00
ef1c1ca821
intel/genxml: Add the preferred slm size enum for xe2
...
Signed-off-by: Rohan Garg <rohan.garg@intel.com >
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26390 >
2023-12-01 02:36:12 +00:00
bdb9c70f84
intel/genxml: Update INTERFACE_DESCRIPTOR_DATA for xe2
...
Reworks:
* Caio: Remove "Mask Stack Exception Enable", not present in BSpec.
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com >
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26390 >
2023-12-01 02:36:12 +00:00
aafdf59dfe
intel/genxml: Update COMPUTE_WALKER for xe2
...
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com >
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26390 >
2023-12-01 02:36:12 +00:00
7a9e82e82f
genxml/12.5: Add the EXECUTE_INDIRECT_DISPATCH instruction
...
Signed-off-by: Rohan Garg <rohan.garg@intel.com >
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26421 >
2023-11-30 17:01:45 +00:00
4229757309
genxml/12.5: Add the EXECUTE_INDIRECT_DRAW instruction
...
Signed-off-by: Rohan Garg <rohan.garg@intel.com >
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26421 >
2023-11-30 17:01:44 +00:00
544c5c006c
intel/genxml: add the Gen12+ TR-TT registers
...
These are the registers we're going to use for now.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26036 >
2023-11-04 02:06:52 +00:00
f0d24b155b
intel/xehp+: Adjust TBIMR batch size based on slice count.
...
This programs a TBIMR batch size equal to 128 polygons per slice in
order to match the hardware spec recommendation (BSpec 68436). This
has been confirmed to improve performance slightly relative to the
hardware default batch size of 256 polygons.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25493 >
2023-10-27 14:50:42 -07:00
7cdacaf493
intel/xehp: Adjust TBIMR performance chicken bits.
...
This enables a couple of TBIMR performance tunables in
CHICKEN_RASTER_2 that default to disabled. TBIMR fast clip appears to
help slightly with some geometry-bound workloads. TBIMR open batch
allows the rasterizer to start working immediately on the first tile
of the framebuffer, even before the batch has been closed, which helps
reduce the latency cost of the tile walk.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25493 >
2023-10-27 14:50:42 -07:00
cec5541b02
intel/xehp+: Add TBIMR-related genxml definitions.
...
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25493 >
2023-10-27 14:48:29 -07:00
26c2c96d62
anv: enable FCV for Gen12.5
...
Now that we have proper handling of FCV_CCS_E everywhere, we can turn
this on for Gen12.5.
This helps fix a performance regression where enabling fast
clears to non-zero values with CCS_E caused additional partial resolves,
regressing performance on certain games. Performance is helped on the
following games:
- F1'22: +45%
- RDR2: +6%
Signed-off-by: Rohan Garg <rohan.garg@intel.com >
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25589 >
2023-10-11 12:18:15 +00:00
300c98dbb2
intel/genxml: fix 3DSTATE_3D_MODE length to align with BSpec
...
Closes : #8632
Fixes: 569afd37f1rohan.garg@intel.com >
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25589 >
2023-10-11 12:18:15 +00:00
1c4d57568a
intel/genxml: remove HDC from gen11.xml, it is not available
...
Signed-off-by: Tapani Pälli <tapani.palli@intel.com >
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25399 >
2023-10-02 12:05:54 +00:00
961aa68b23
intel/genxml: Build with gen20.xml
...
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com >
Reviewed-by: José Roberto de Souza <jose.souza@intel.com >
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25253 >
2023-09-21 18:24:01 +00:00
6f1b1d6330
intel/genxml: Auto-import genxml files using genxml_import.py
...
$ src/intel/genxml/genxml_import.py --import
This can be reversed with:
$ src/intel/genxml/genxml_import.py --flatten
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com >
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20593 >
2023-09-14 11:05:16 -07:00
cd0c758f32
intel/genxml: Start Xe2 support
...
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com >
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20593 >
2023-09-14 11:05:16 -07:00
0495f952d4
intel/genxml: Add genxml_import.py script
...
This script can:
* validate that genxml files do not duplicate imported items
* add imports to genxml files and optimize the file by dropping
duplicate items
* reverse the import operation by flattening genxml files
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com >
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20593 >
2023-09-14 11:05:16 -07:00
6ad2f39bab
intel/genxml: Add GenXml.flatten_xml() method
...
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com >
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20593 >
2023-09-14 11:05:16 -07:00
c0f7feb239
intel/genxml: Add GenXml.add_xml_imports method
...
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com >
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20593 >
2023-09-14 11:05:16 -07:00
Rohan Garg