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186546 Commits

Author SHA1 Message Date
Mike Blumenkrantz 20013a1774 radv: stop blocking non-2D import/export ops 
these work fine

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33323>
 2025-02-06 01:48:25 +00:00
Mike Blumenkrantz ca8a740e3b radv: fix error reporting for VkExternalMemoryTypeFlagBitsKHR 
wrong type name is confusing

cc: mesa-stable

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33323>
 2025-02-06 01:48:25 +00:00
Mike Blumenkrantz 602f19bad8 ac/surface: always allow LINEAR modifier for color formats 
this is always supported

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33323>
 2025-02-06 01:48:25 +00:00
Caio Oliveira 1ade9a05d8 intel/brw: Use brw prefix instead of namespace for analysis implementations 
Also drop the 'fs' prefix when applicable.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33048>
 2025-02-05 21:47:07 +00:00
Caio Oliveira 2b92eb0b2c intel/brw: Use brw prefix instead of namespace for dep analysis enum 
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33048>
 2025-02-05 21:47:07 +00:00
Caio Oliveira e2f354587d intel/brw: Merge brw_ir_analysis.h into brw_analysis.h 
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33048>
 2025-02-05 21:47:07 +00:00
Caio Oliveira c943fb0c20 intel/brw: Move analysis passes without own file to brw_analysis.cpp 
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33048>
 2025-02-05 21:47:06 +00:00
Caio Oliveira 0f7eb96af8 intel/brw: Move idom_tree declaration to brw_analysis.h 
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33048>
 2025-02-05 21:47:06 +00:00
Caio Oliveira 0ebb75743d intel/brw: Use brw_analysis prefix for performance analysis files 
Move declaration to the common header and rename definition file.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33048>
 2025-02-05 21:47:06 +00:00
Caio Oliveira 6a23749332 intel/brw: Use brw_analysis prefix for def analysis file 
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33048>
 2025-02-05 21:47:06 +00:00
Caio Oliveira e0614e8ea1 intel/brw: Use brw_analysis prefix for liveness analysis files 
Move declaration to the common header and rename definition file.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33048>
 2025-02-05 21:47:06 +00:00
Caio Oliveira e5369540ea intel/brw: Add brw_analysis.h 
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33048>
 2025-02-05 21:47:06 +00:00
Alyssa Rosenzweig bf48eae1f9 nir: drop printf_base_identifier 
superseded.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33380>
 2025-02-05 20:33:15 +00:00
Alyssa Rosenzweig e3bc6eafc8 nir/lower_printf: hash format strings in nir_printf_fmt 
Lionel added a neat debugging tool. Let's make it work with the new-style
hashing approach too, since nir_printf_fmt is a lot more convenient than needing
to define a dedicated CL function to access printf (although that works too).

We remove the old non-hashed path, because it has no more functional users --
hashing is a hard requirement with vtn_bindgen2, which Intel has now switched
to.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33380>
 2025-02-05 20:33:15 +00:00
Alyssa Rosenzweig 41eabbadfa intel: port to u_printf context + singleton 
this is required with vtn_bindgen2. fixes printf there.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33380>
 2025-02-05 20:33:15 +00:00
Alyssa Rosenzweig 9429d001b9 intel/nir_lower_printf: modernize nir 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33380>
 2025-02-05 20:33:15 +00:00
Alyssa Rosenzweig 03ff5b2c03 intel: drop nir_lower_printf calls 
this is now handled in vtn_bindgen2 for vtn path code. this does drop support
from printf from GRL but that seems appropriate at this point.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33380>
 2025-02-05 20:33:15 +00:00
Alyssa Rosenzweig 07ccaa3118 Revert "hk: Stop using strings or common key types for meta keys" 
This reverts commit 32e0e8c8c5, which broke the
build on Honeykrisp (and then the obvious build fix causes CTS to blow up with
explosions).

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33406>
 2025-02-05 20:01:35 +00:00
Eric Engestrom 93a720f81a gfxstream: mark unused variables as such 
It's unclear to me whether this is dead code that should be removed or
dead code that should be used, so I just marked it as unused to remove
a few thousand warnings when compiling.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33384>
 2025-02-05 19:28:42 +00:00
Eric Engestrom b2b37cb1de gfxstream: use range variable for its intended purpose 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33384>
 2025-02-05 19:28:42 +00:00
Eric Engestrom 96c183c759 gfxstream: drop dead variables 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33384>
 2025-02-05 19:28:42 +00:00
Eric Engestrom 74d0a8cdd6 gfxstream: fix signedness of shifts 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33384>
 2025-02-05 19:28:42 +00:00
Eric Engestrom 58938f7348 gfxstream: drop unnecessary semi-colons 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33384>
 2025-02-05 19:28:41 +00:00
Alyssa Rosenzweig 0ce0b7c7b0 hk: advertise EXT_image_view_min_lod 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33386>
 2025-02-05 17:27:18 +00:00
Alyssa Rosenzweig 157ffa5b43 hk: emulate EXT_image_view_min_lod 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33386>
 2025-02-05 17:27:18 +00:00
Alyssa Rosenzweig 8e1ce5331b hk: rearrange sampler image desc 
pack nicer.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33386>
 2025-02-05 17:27:18 +00:00
Alyssa Rosenzweig 7ed6aa68ad hk: pack has_border with clamp_0_sampler_index 
this is cheaper to decode (shorter preambles!).

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33386>
 2025-02-05 17:27:18 +00:00
Alyssa Rosenzweig 6e29a2c8d5 agx: switch to nir_tex_src_lod_bias_min_agx 
saves moves.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33386>
 2025-02-05 17:27:18 +00:00
Alyssa Rosenzweig 932d8a68eb agx: lower min LOD for txf 
to match the robustness semantic the spec wants.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33386>
 2025-02-05 17:27:18 +00:00
Alyssa Rosenzweig 780b814354 nir: add lod_bias_min_agx tex src 
this lets nir_opt_preamble Just Do The Right thing, so model in NIR

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Acked-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33386>
 2025-02-05 17:27:18 +00:00
Alyssa Rosenzweig c5de33e48e nir: add image_min_lod_agx 
for EXT_image_view_min_lod emulation.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Acked-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33386>
 2025-02-05 17:27:18 +00:00
Samuel Pitoiset 4fc856af98 radv: fix caching on-demand meta shaders 
This switches to disk_cache instead of our own mechanism which only
stored meta shaders when the logical was destroyed.

Meta shaders are still stored separately from the application shaders
because they are common to all applications on a given GPU/Mesa version.
The default cache is 32MiB which should be large enough.

This fixes massive stuttering in FF7 Rebirth but all apps are
technically affected.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33370>
 2025-02-05 16:30:27 +00:00
Samuel Pitoiset 9d03c1afe0 vulkan/runtime: allow to use a different disk cache 
Instead of using the default one provided by the physical device.
This will be used by RADV to store meta shaders to a separate single
cache file.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33370>
 2025-02-05 16:30:27 +00:00
Samuel Pitoiset 30961b2bfe util/disk_cache: add a new helper to create a disk cache 
This will be used by RADV to store the meta shaders to a separate
cache directory.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33370>
 2025-02-05 16:30:27 +00:00
Job Noorman 8404e7428b ir3: fix emitting descriptor prefetches at end of preamble 
The fix in e7ac1094f6 to emit preamble defs in the correct block would
move the cursor of the builder that is later used to insert descriptor
prefetches, emitting them at the wrong place. Fix this by resetting the
cursor before emitting the prefetches.

Signed-off-by: Job Noorman <jnoorman@igalia.com>
Fixes: e7ac1094f6 ("ir3: rematerialize preamble defs in block dominated by sources")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33399>
 2025-02-05 14:58:38 +00:00
Valentine Burley e192d7d615 intel/ci: Update expectations for Xe 
Signed-off-by: Valentine Burley <valentine.burley@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33282>
 2025-02-05 14:01:03 +00:00
Valentine Burley 12ddff54ba intel/ci: Use INTEL_XE_IGNORE_EXPERIMENTAL_WARNING to reduce warnings 
Signed-off-by: Valentine Burley <valentine.burley@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33282>
 2025-02-05 14:01:03 +00:00
Valentine Burley 0d1fa0f1a3 intel/dev: Provide a toggle to avoid warnings about unsupported devices 
Signed-off-by: Valentine Burley <valentine.burley@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33282>
 2025-02-05 14:01:03 +00:00
Valentine Burley fcd5d25888 intel/ci: Load Xe instead of i915 on ADL 
Xe doesn't probe on ADL without being explicitly forced through cmdline
arguments.

Signed-off-by: Valentine Burley <valentine.burley@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33282>
 2025-02-05 14:01:03 +00:00
Valentine Burley f736f19642 intel/ci: Drop redundant BOOT_METHOD variables 
The BOOT_METHOD is defined in .intel-common-test, which every Intel
job inherits, including the zink jobs.

Signed-off-by: Valentine Burley <valentine.burley@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33282>
 2025-02-05 14:01:03 +00:00
Mary Guillemard e3b8d1da6d panvk: Disallow unknown GPU models early in physical device init 
We rely on the panfrost_model details around the codebase, if it's not
known this is a problem.

As a result, we will now disallow anything that isn't known like what
we do on Gallium.

Fixes: c95ef9e323 ("panvk: Fix NULL deref on model name when device isn't supported")
Signed-off-by: Mary Guillemard <mary.guillemard@collabora.com>
Suggested-by: Lars-Ivar Hesselberg Simonsen <lars-ivar.simonsen@arm.com>
Reviewed-by: Lars-Ivar Hesselberg Simonsen <lars-ivar.simonsen@arm.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33371>
 2025-02-05 13:30:29 +00:00
Mary Guillemard 0e7ac7d65f panfrost: Properly name CSF instruction UMIN32 source 0 
Was named source 2, but it's actually source 0.

Signed-off-by: Mary Guillemard <mary.guillemard@collabora.com>
Reviewed-by: Lars-Ivar Hesselberg Simonsen <lars-ivar.simonsen@arm.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33371>
 2025-02-05 13:30:29 +00:00
Mary Guillemard 7bb6ebe938 pan/decode: Fix indirect branch calculation for 64-bit 
THe enum variant for u64 was actually 32-bit making all 64-bit operation
wrong.

Signed-off-by: Mary Guillemard <mary.guillemard@collabora.com>
Fixes: 7d0dc3d30c ("pan/decode: Add a helper to print CS binaries without interpreting them")
Reviewed-by: Lars-Ivar Hesselberg Simonsen <lars-ivar.simonsen@arm.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33371>
 2025-02-05 13:30:29 +00:00
Mary Guillemard 135aeddc9b pan/bi: Use 2D dimension with TEX_FETCH with CUBE on Valhall 
TEX_FETCH doesn't have the CUBE dimension, this was working on v9 and
v10 but this fails on Avalon.

Signed-off-by: Mary Guillemard <mary.guillemard@collabora.com>
Fixes: ce52b6d359 ("pan/bi: Rework indices for tex on Valhall")
Reviewed-by: Lars-Ivar Hesselberg Simonsen <lars-ivar.simonsen@arm.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33371>
 2025-02-05 13:30:29 +00:00
Mary Guillemard c36326d3af pan/bi: Remove b3210 from valid swizzle 
This was removed on v11, we currently don't use it so to ensure no one
start using it, let's just mark it as reserved.

Signed-off-by: Mary Guillemard <mary.guillemard@collabora.com>
Reviewed-by: Lars-Ivar Hesselberg Simonsen <lars-ivar.simonsen@arm.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33371>
 2025-02-05 13:30:29 +00:00
Mary Guillemard b00c09b920 pan/bi: Fix invalid CLPER encoding 
This src1 expect lanes, isn't widen and have a size of 8-bit (5-bit on
Valhall, 4-bit on Avalon)

We also now disallow swizzle lowering on it. (even on Bifrost)

Fixes: 316486dd9f ("pan/va: Add initial ISA.xml for Valhall")
Signed-off-by: Mary Guillemard <mary.guillemard@collabora.com>
Reviewed-by: Lars-Ivar Hesselberg Simonsen <lars-ivar.simonsen@arm.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33371>
 2025-02-05 13:30:29 +00:00
Mary Guillemard 637cb0a993 pan/bi: Remove shift lanes invalid encodings 
We were wrongly defining values that select more than one byte.

The swizzle used for H01 was working fine for v9 and v10, but this
generate an invalid encoding on Avalon.

This fixes this by using B00 variant as we are only using 8-bit sources.

Fixes: f45654af59 ("pan/va: Add packing routines")
Signed-off-by: Mary Guillemard <mary.guillemard@collabora.com>
Reviewed-by: Lars-Ivar Hesselberg Simonsen <lars-ivar.simonsen@arm.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33371>
 2025-02-05 13:30:29 +00:00
Mary Guillemard fbd5d58e36 pan/bi: Properly encode LEA_BUF_IMM 
We were hardcoding table 61 and index 0 for IDVS based usage and this
could have been misused.

Signed-off-by: Mary Guillemard <mary.guillemard@collabora.com>
Fixes: f45654af59 ("pan/va: Add packing routines")
Reviewed-by: Lars-Ivar Hesselberg Simonsen <lars-ivar.simonsen@arm.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33371>
 2025-02-05 13:30:29 +00:00
Mary Guillemard 38a3cd8c76 panfrost: Fix PROGRESS_LOAD destination register 
The offset of dest should be 40, not 48.

Signed-off-by: Mary Guillemard <mary.guillemard@collabora.com>
Fixes: 486c341769 ("panfrost: Add architecture description XML for v10")
Reviewed-by: Lars-Ivar Hesselberg Simonsen <lars-ivar.simonsen@arm.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33371>
 2025-02-05 13:30:29 +00:00
Mary Guillemard 05c2abcfea panfrost: Fix group priorities in drm-shim 
Those were supposed to use BITFIELD_BIT.

Fixes: 2237cff1af ("panfrost: Report default value for GROUP_PRIORITIES_INFO in drm-shim")
Signed-off-by: Mary Guillemard <mary.guillemard@collabora.com>
Reviewed-by: Lars-Ivar Hesselberg Simonsen <lars-ivar.simonsen@arm.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33371>
 2025-02-05 13:30:29 +00:00