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Author SHA1 Message Date
Jason Ekstrand eea49c7d32 hasvk: Drop SKL+ features 
Most of these have already had all the code removeed.  We just need to
remove the feature bits and queries.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19852>
 2022-12-02 09:18:17 +00:00
Jason Ekstrand b71ac720a8 hasvk: Drop support for atomic_int64 and atomic_float2 
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19852>
 2022-12-02 09:18:17 +00:00
Jason Ekstrand 49201fe8c1 hasvk: Drop bindless image support 
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19852>
 2022-12-02 09:18:17 +00:00
Jason Ekstrand 7b700369b1 hasvk: Drop A64 descriptor set support 
It's only used by task/mesh and ray-tracing.  Also drop a couple
remaining ray query things and a task/mesh we left behind.

v2: Fix incorrect use of nir_load_desc_set_address_intel (Lionel)

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19852>
 2022-12-02 09:18:17 +00:00
Jason Ekstrand 85cfa21e04 hasvk: Drop remnants of ray queries 
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19852>
 2022-12-02 09:18:17 +00:00
Jason Ekstrand e490434479 hasvk: Drop CCS_E support 
Oh, for the days of Broadwell and earlier where compression was called
fast-clear.  That was a simpler time.  The birds sang in the trees, the
oceans weren't brown from oil spills, and Intel surface compression was
actually comprehendable by humans.  To help the reviewer, keep the
following in mind:

 1. CCS_E is SKL+
 2. Implicit CCS is TGL+
 3. The AUX TT (AKA aux map) is TGL+
 4. HIZ+CCS, stencil CCS, and CCS for storage images are all TGL+
 4. CCS_D surfaces only ever get full resolves and MCS surfaces only
    ever get partial resolves

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19852>
 2022-12-02 09:18:17 +00:00
Jason Ekstrand 5f1dbd80b3 hasvk: Rip out primitive replication 
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19852>
 2022-12-02 09:18:17 +00:00
Jason Ekstrand 7f97cd04c9 hasvk: Rip out remaining traces of CPS/FSR 
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19852>
 2022-12-02 09:18:17 +00:00
Jason Ekstrand 90aab6e9a5 hasvk/gpu_memcpy: Rip out SKL+ 
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19852>
 2022-12-02 09:18:16 +00:00
Jason Ekstrand 6d80ce1283 hasvk/state: Rip out SKL+ 
v2: Fix incorrectly removed l3cr.SLMEnable setting (Lionel)

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19852>
 2022-12-02 09:18:16 +00:00
Jason Ekstrand ce57cc4397 hasvk/blorp: Rip out SKL+ 
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19852>
 2022-12-02 09:18:16 +00:00
Jason Ekstrand cc68b7cd94 hasvk/pipeline: Rip out SKL+ 
v2: Fix incorrect DispatchMode removal (Lionel)

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19852>
 2022-12-02 09:18:16 +00:00
Jason Ekstrand 91090e39af hasvk/cmd_buffer: Rip out SKL+ support 
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19852>
 2022-12-02 09:18:16 +00:00
Lionel Landwerlin 0626b68c88 isl: don't report I915_FORMAT_MOD_Y_TILED_CCS on Gfx8 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: mesa-stable
Acked-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19852>
 2022-12-02 09:18:16 +00:00
Lionel Landwerlin a855bdbf47 intel/nir/rt: switch to workgroup_id_zero_base 
RT don't use a base workgroup id so no reason of using workgroup_id.
Additionally the lowering introduced in b4dd3df227 requires something
provides base_workgroup_id which we don't have for RT as it's not
needed.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: b4dd3df227 ("intel/nir: Set has_base_workgroup_id for lower_compute_system_values")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/7812
Reviewed-by: Mark Janes <markjanes@swizzler.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20115>
 2022-12-02 05:25:22 +00:00
Jordan Justen 686ada78cd intel/dev: Add (disabled) device info for MTL 
Reworks:
 * Jordan: INTEL_PLATFORM_MTL_M/INTEL_PLATFORM_MTL_P
 * Lionel: .has_coarse_pixel_primitive_and_cb
 * Jordan: .has_mesh_shading & .has_ray_tracing
 * Paulo: .has_64bit_float
 * José: .has_integer_dword_mul (BSpec: 47431)
 * Jordan: Comment pci device ids for now similar to DG2:
   * 70a4e64685 ("intel: Add *disabled* device ids for DG2")
   * ad565f6b70 ("intel/dev: Enable first set of DG2 PCI IDs")

Ref: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/include/drm/i915_pciids.h?h=v6.0-rc4#n736
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19658>
 2022-12-01 16:22:47 +00:00
Marcin Ślusarz db0e6f9a07 intel/compiler: user payload starts after TUE header & its padding 
All data written by the user are offset by TUE header size.
Without this patch we copy the correct amount of user data, but both
"from" and "to" offsets are wrong.

Fixes: 37e78803d7 ("intel/compiler: use nir_lower_task_shader pass")

Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19409>
 2022-12-01 11:19:47 +00:00
Marcin Ślusarz 7aaafaa8ae intel/compiler: adjust [store|load]_task_payload.base too 
Base also needs to be converted from bytes to words.

Fixes: c36ae42e4c ("intel/compiler: Use nir_var_mem_task_payload")
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19409>
 2022-12-01 11:19:47 +00:00
Jason Ekstrand 216e5d6e10 hasvk: Drop anv_nir_add_base_work_group_id() 
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20068>
 2022-12-01 04:56:48 +00:00
Jason Ekstrand 2806968af8 anv: Drop anv_nir_add_base_work_group_id() 
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20068>
 2022-12-01 04:56:48 +00:00
Jason Ekstrand b4dd3df227 intel/nir: Set has_base_workgroup_id for lower_compute_system_values 
This option didn't exist half a decade ago when I first implemented base
workgroup support in ANV.  It's cleaner to just have split system values
like all the other zero_base+base things do.

We currently only do this for COMPUTE and not KERNEL because it lets us
avoid changing intel_clc for now.  We can add KERNEL later if needed.
We also don't do this lowering for task/mesh.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20068>
 2022-12-01 04:56:48 +00:00
Jason Ekstrand 19ad2629d0 hasvk: Implement lower_base_workgroup_id 
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20068>
 2022-12-01 04:56:48 +00:00
Jason Ekstrand 3c09571f67 anv: Implement lower_base_workgroup_id 
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20068>
 2022-12-01 04:56:48 +00:00
Jason Ekstrand 7d2e3f660c intel/fs: Support load_workgroup_id_zero_base 
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20068>
 2022-12-01 04:56:48 +00:00
Jason Ekstrand d9a24632d3 nir/builder: Drop nir_i2i and nir_u2u in favor of nir_x2xN 
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20067>
 2022-12-01 01:10:12 +00:00
Yonggang Luo 871443f4de ci: Add intel kbl xfail to flake 
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/7738

Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19860>
 2022-11-30 17:24:03 +00:00
Lionel Landwerlin 6f2dbe6da1 anv: enable lower_shader_calls vectorizing 
On Q2RTX RT shaders :

Totals from 7 (22.58% of 31) affected shaders:
Instrs: 15453 -> 14418 (-6.70%)
Cycles: 232647 -> 224959 (-3.30%)
Send messages: 574 -> 481 (-16.20%)
Spill count: 118 -> 106 (-10.17%)
Fill count: 156 -> 140 (-10.26%)

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20058>
 2022-11-30 07:23:30 +00:00
Aditya Swarup 6080dce4d8 intel/isl: Add MOCS settings for MTL platforms 
Add MOCS settings for Xe platforms based on cache settings for L3/L4
and display.

Rework:
 * Jordan: Use intel_device_info_is_mtl()

BSpec: 45101
Signed-off-by: Aditya Swarup <aditya.swarup@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20045>
 2022-11-29 00:36:41 -08:00
Jianxun Zhang 93baad8047 intel/dev: Set 'has_flat_ccs' flag for DG2 
The code paths of flat ccs should be working on DG2 because
they are routed by other conditions like GFXVer so far. But
using this flag is the intended way, and we need to have
this change prior to updating these conditions with the flag.

Ref: 5262475242 ("intel/dev: Add a has_flat_ccs flag")

Signed-off-by: Jianxun Zhang <jianxun.zhang@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20043>
 2022-11-29 02:47:44 +00:00
Jordan Justen 4db33adf9d intel/isl: Disable CCS on MTL 
MTL requires some ccs/aux-map changes from Jianxun Zhang, which are
still in progress. So, for now we disable ccs on MTL.

Rework:
 * Drop change in isl_surf_supports_ccs (Nanley)

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20046>
 2022-11-28 17:09:52 -08:00
Jordan Justen cbae305258 anv, iris: Make use of devinfo::has_caching_uapi 
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19911>
 2022-11-28 21:54:20 +00:00
Jordan Justen ed84f163ff intel/dev: Add devinfo::has_caching_uapi (and disable for dg1 and dg2+) 
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19911>
 2022-11-28 21:54:20 +00:00
Martin Roukala (né Peres) 0cee008fee Revert "glx: Fix drawable refcounting for naked Windows" 
This reverts commit 768238fdc0 which
is not only leading to memory leaks, but also reportedly breaks KDE
pretty badly.

Fixes: #7674, #7435
Acked-by: Michel Dänzer <mdaenzer@redhat.com>
Acked-by: Tapani Pälli <tapani.palli@intel.com>
Acked-by: Adam Jackson <ajax@redhat.com>
Signed-off-by: Martin Roukala (né Peres) <martin.roukala@mupuf.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19972>
 2022-11-25 20:08:45 +00:00
Lionel Landwerlin bbbc8e7ce7 anv: use the anv_state_pool address helper more 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19983>
 2022-11-25 10:29:56 +00:00
Hans-Kristian Arntzen 4889be3883 anv: Conditionally expose VK_KHR_present_wait on ANV. 
Gate it behind driconf query for now.

Signed-off-by: Hans-Kristian Arntzen <post@arntzen-software.no>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19279>
 2022-11-23 19:06:12 +00:00
LingMan 11f91505d9 intel/fs: Accept an unsigned int in fs_reg::fs_reg 
The parameter `nr` is currenlty an `int` but it only gets assigned to an
`unsigned int`. Make it clear in the function signature what's actually
required.

Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19423>
 2022-11-23 18:37:35 +00:00
LingMan fc00314085 intel/fs: Preserve unsignedness in fs_visitor::split_virtual_grfs 
GCC 12.2.0 warns:
../src/intel/compiler/brw_fs.cpp: In member function ‘bool fs_visitor::
split_virtual_grfs()’:
../src/intel/compiler/brw_fs.cpp:2199:10: warning: ‘void* memset(void*, int,
size_t)’ specified size between 18446744071562067968 and 18446744073709551615
exceeds maximum object size 9223372036854775807 [-Wstringop-overflow=]
 2199 |    memset(vgrf_has_split, 0, num_vars * sizeof(*vgrf_has_split));

`num_vars` is an `int` but gets assigned the value of `this->alloc.count`,
which is an `unsigned int`. Thus, `num_vars` will be negative if
`this->alloc.count` is larger than int max value. Converting that negative
`int` to a `size_t`, which `memset` expects, then blows it up to a huge
positive value.

Simply turning `num_vars` into an `unsigned int` would be enough to fix this
specific problem, but there are many other instances where an `unsigned int`
gets assigned to an `int` for no good reason in this function. Some of which
the compiler warns about now, some of which it doesn't warn about.

This turns all variables in `fs_visitor::split_virtual_grfs`, which should
reasonably be unsigned, into `unsigned int`s. While at it, a few now pointless
casts are removed.

Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19423>
 2022-11-23 18:37:35 +00:00
Philippe Lecluse bd2dd03937 intel: Disable SSE2 instruction set if building for non x86 architectures 
Signed-off-by: Philippe Lecluse <philippe.lecluse@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19812>
 2022-11-23 16:57:23 +00:00
Philippe Lecluse a821dfbda5 intel: Add SUPPORT_INTEL_INTEGRATED_GPUS build argument 
This is meant to remove any integrated GPU only code paths that can't
be compiled in CPU architectures different than x86.

Discrete GPUS don't have need_clflush set to true so it was just
matter of remove some code blocks around need_clflush but was left a
check in anv_physical_device_init_heaps() to fail physical device
initialization if it ever became false.

Signed-off-by: Philippe Lecluse <philippe.lecluse@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19812>
 2022-11-23 16:57:23 +00:00
Lionel Landwerlin 9bb055ff5d anv: generate correct addresses for state pool offsets 
Fixes a number of CTS patterns on DG2 :

   - dEQP-VK.dynamic_rendering.primary_cmd_buff.random*
   - dEQP-VK.draw.*secondary_cmd*
   - dEQP-VK.dynamic_rendering.*secondary_cmd*
   - dEQP-VK.geometry.*secondary_cmd_buffer
   - dEQP-VK.multiview.*secondary_cmd*

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: 9c1c1888d9 ("intel/fs: put scratch surface in the surface state heap")
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19946>
 2022-11-23 14:37:19 +00:00
Lionel Landwerlin 20e8e1eb06 blorp: support negative offsets in addresses 
Similar to anv_address

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: 9c1c1888d9 ("intel/fs: put scratch surface in the surface state heap")
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19946>
 2022-11-23 14:37:19 +00:00
Lionel Landwerlin 1d9608be1a genxml: forbid usage of L1CC_WBP/L1CC_UC for stateless messages 
We want to avoid those settings so that we do not have to emit a tile
fence to implement Wa_22013689345.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19322>
 2022-11-23 06:54:04 +00:00
Lionel Landwerlin 945637514e intel/fs: improve Wa_22013689345 workaround 
The initial implementation is a pretty big hammer. Implement the HW
recommendation to minimize cases in which we need a fence.

This improves by 10FPS on some of the Sascha Willems RT demos.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: 6031ad4bf6 ("intel/fs: Add Wa_22013689345")
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19322>
 2022-11-23 06:54:04 +00:00
Vinson Lee 86f353ed23 intel/perf: Fix memory leak. 
Fix defect with Coverity Scan.

Resource leak (RESOURCE_LEAK)
leaked_storage: Variable pass_array going out of scope leaks the storage it points to.

Fixes: d4cbb66506 ("intel/perf: support more than 64 queries")
Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19888>
 2022-11-22 22:17:02 -08:00
José Roberto de Souza 15c1a9ed60 anv: Set 3DSTATE_RASTER API mode as recomended 
TGL+ specification ask the API mode to be set to DX10.1 for Vulkan API.

BSpec: 46947
Reference: TGL PRMs, Volume 2d: Command Reference: Structures: 3DSTATE_RASTER_BODY
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19934>
 2022-11-23 01:37:07 +00:00
Emma Anholt f4b7b73df4 ci/iris: Drop EGL copyteximage2d.12 xfail. 
It is still marked as a flake (along with other copyteximage cases) on all
these boards, so this will reduce the CI IRC channel noise given that we
actually expect a Pass.  I haven't found where exactly in history we went
from generally-fail to generally-pass, but it looks like around Feb 2022.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19912>
 2022-11-22 21:28:02 +00:00
Emma Anholt 1c59c10deb ci/iris: Add headless Wayland testing using weston. 
Acked-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19912>
 2022-11-22 21:28:02 +00:00
Lionel Landwerlin 3aadbb9fde anv: enable sample location enable dynamic state 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19925>
 2022-11-22 17:04:33 +00:00
Lionel Landwerlin f7d6c6e1ed anv: fixup context initialization on DG2 
Fixing a typo :(

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: 507a86e131 ("anv: ensure CPS is initialized when KHR_fragment_shading_rate is disabled")
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19922>
 2022-11-22 09:26:23 +00:00
Yonggang Luo 40a9fc57aa tree-wide: Use __func__ instead of __FUNCTION__ in non-gallium code 
Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Acked-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Acked-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19861>
 2022-11-22 06:53:46 +00:00