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Author SHA1 Message Date
Ian Romanick 51be623372 intel/eu/validate: Check predication and cmod for SEL, CMP, and CMPN 
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20527>
 2023-01-09 19:15:19 +00:00
Ian Romanick e0f409c5d8 intel/eu/validate: Add validation for csel 
v2: Also check the condition modifier. Suggested by Lionel.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20527>
 2023-01-09 19:15:19 +00:00
Ian Romanick 3a7c23973b intel/eu/validate: Add validation for bfi2 
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20527>
 2023-01-09 19:15:19 +00:00
Ian Romanick f34821d998 intel/eu/validate: More validation for logic ops 
v2: Use number of source to condition validating src1 instead of using
the opcode. Suggested by Lionel.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20527>
 2023-01-09 19:15:19 +00:00
Ian Romanick 8be7406c81 intel/compiler: Assert that ARF used is the accumulator 
v2: Move the new check to be with similar existing checks. Suggested by
Lionel.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20527>
 2023-01-09 19:15:19 +00:00
Ian Romanick 3b579a2ea8 intel/compiler: Validate 3-source instruction source strides 
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20527>
 2023-01-09 19:15:19 +00:00
Ian Romanick c5684019f6 intel/compiler: Validate 3-source instruction sources have same base type 
This can't be checked in EU validation because the bits to describe the
base type of the individual sources no longer exist.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20527>
 2023-01-09 19:15:19 +00:00
José Roberto de Souza 1067ec90a5 anv: Update PIPELINE_CONTROL flush when switching pipeline mode in TGL+ 
This 2 PIPELINE_CONTROL flushes are not necessary for TGL and newer
and also it have different requirements of flush, so here doing
this two changes at the same time.

As no ANV_PIPE_INVALIDATE_BITS is set as parameter of
anv_add_pending_pipe_bits(),
genX(cmd_buffer_apply_pipe_flushes)(cmd_buffer) will only emit one
PIPELINE_CONTROL.

BSpec: 44505
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20501>
 2023-01-09 14:40:26 +00:00
Lionel Landwerlin 6b494745be intel/fs: only avoid SIMD32 if strictly inferior in throughput 
This enabled SIMD32 in blorp shaders and seems to be give a small FPS
bump when using a DG2 GPU as secondary (requires copies to linear
buffers to exchange with main GPU).

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19341>
 2023-01-09 08:41:47 +00:00
Rohan Garg 85650297d2 anv,hasvk: move the null check into the function call and drop null check copies 
Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20104>
 2023-01-06 17:22:16 +00:00
Rohan Garg 0ae23b81a4 anv: Drop useless FIXME 
Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20104>
 2023-01-06 17:22:16 +00:00
Rohan Garg 00ffe8227f anv,hasvk: drop unused function 
align_i32 is not used anywhere

Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20104>
 2023-01-06 17:22:16 +00:00
Rohan Garg 05dca17b57 anv,hasvk: migrate to ROUND_DOWN_TO from util 
Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20104>
 2023-01-06 17:22:16 +00:00
Rohan Garg 818eed3d2f anv,hasvk: migrate to u_minify from util 
Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20104>
 2023-01-06 17:22:16 +00:00
Rohan Garg 9257b08f49 anv: migrate anv_minify to use u_minify 
Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20104>
 2023-01-06 17:22:16 +00:00
Rohan Garg 4504188508 anv,hasvk: migrate to align64 from util 
Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20104>
 2023-01-06 17:22:16 +00:00
Rohan Garg a06f751ec8 anv,hasvk: migrate align32 to the right functions from util 
Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20104>
 2023-01-06 17:22:16 +00:00
Rohan Garg 1e9fb7c696 anv,hasvk: Use the inbuilt macro from src/util for clamping int64_t 
Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20104>
 2023-01-06 17:22:15 +00:00
Rohan Garg 0030d6d224 anv: constify variables and use early returns 
Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20104>
 2023-01-06 17:22:15 +00:00
Max Lee 32010d985c intel_noop_drm_shim: add ability to specify device id 
Given a GPU platform, there are multiple device ids. This commit
adds ability to specify device id for the shim, instead of using
one of the hard-coded device ids per platform.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20526>
 2023-01-05 08:37:01 +00:00
Felix DeGrood c1c81137d9 hasvk: Emit CS stall on INTEL_MEASURE timestamp 
For INTEL_MEASURE, ensure all prior instructions completed before
timestamp taken. Continue to support no CS flush case for Perfetto.
CS stall was dropped from pipecontrol when adding u_trace support.

Fixes: cc5843a573 ("anv: implement u_trace support")
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20502>
 2023-01-04 22:43:36 +00:00
Felix DeGrood 7f6beb8537 anv: Emit CS stall on INTEL_MEASURE timestamp 
For INTEL_MEASURE, ensure all prior instructions completed before
timestamp taken. Continue to support no CS flush case for Perfetto.
CS stall was dropped from pipecontrol when adding u_trace support.

Fixes: cc5843a573 ("anv: implement u_trace support")
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20502>
 2023-01-04 22:43:36 +00:00
Emma Anholt 01b5e876a2 ci/iris: Add some recent flakes. 
APL are clearly part of the existing set, glx-swap-copy on KBL is
plausibly new but it's a flake on other drivers too.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20503>
 2023-01-04 21:18:08 +00:00
Ian Romanick 8ab7ec0129 intel/compiler: Enable lower_bitfield_extract_to_shifts and lower_bitfield_insert_to_shifts for pre-Gfx7 
GLSL IR opcodes generated for bitfieldExtract and bitfieldInsert are
lowered by lower_instructions.  4dff3ff005 ("nir/opt_algebraic:
Optimize open coded bfm.") adds an optimization that can rematerialize
nir_op_bfm that was prevented by the GLSL IR lowering.

It appears that every piece of hardware, except older Intel GPUS, that
has real integers (i.e., lower_bitops is not set) also sets
lower_bitfield_extract_to_shifts and lower_bitfield_insert_to_shifts.

Reviewed-by: Emma Anholt <emma@anholt.net>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Fixes: 4dff3ff005 ("nir/opt_algebraic: Optimize open coded bfm.")
Closes: #7874
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20323>
 2023-01-03 18:37:53 -08:00
Emma Anholt 0cff5d51ac ci/intel: Switch skqp testing over to deqp-runner. 
The skqp runner gets us parallel execution, automatic caselist handling,
nice reports, and the same xfail/flake handling you know and love from
deqp and piglit.

And, now that we have flake handling, we can turn the tests back on!

Reviewed-by: Guilherme Gallo <guilherme.gallo@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20070>
 2023-01-04 00:34:33 +00:00
Tapani Pälli 97f2b60833 anv: implement Wa_14015814527 for task shaders 
After using task shader, we need to emit a zero URB state and a
nullprim (empty pipe control) before rendering with primitives.

After this, a normal URB state needs to be returned, this will
happen when pipeline batch is emitted during pipeline switch.

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20334>
 2023-01-03 12:44:08 +00:00
Sviatoslav Peleshko 261a334509 hasvk: Add layer with work-around for Doom 64 texture corruption 
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/7817
Signed-off-by: Sviatoslav Peleshko <sviatoslav.peleshko@globallogic.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19502>
 2023-01-02 15:05:06 +00:00
Sviatoslav Peleshko c2acd9f76a anv: Add layer with work-around for Doom 64 texture corruption 
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/7817
Signed-off-by: Sviatoslav Peleshko <sviatoslav.peleshko@globallogic.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19502>
 2023-01-02 15:05:06 +00:00
José Roberto de Souza def474e916 intel/genxml/gen12.5: Pipe_Control::Remove Global Snapshot Count Reset 
It was not meant to be used(Iris have assert for it) and it was
removed from Pipe_Control instruction in gen12.5 and newer.

BSpec: 47112
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20444>
 2022-12-29 08:34:25 -08:00
José Roberto de Souza c6d1f76da2 anv: Add and use emit_pipeline_select() 
To avoid the replication of code to properly emit PIPELINE_SELECT.

init_compute_queue_state() had a different emit of PIPELINE_SELECT but
as there is no compute engine in GFX VER 11 we are safe with the
differences.

Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20444>
 2022-12-29 08:34:15 -08:00
David Heidelberg 57f73d097e ci/iris: add iris-kbl flake 
Ref: https://gitlab.freedesktop.org/mesa/mesa/-/issues/7547

Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20448>
 2022-12-28 23:08:37 +00:00
Tapani Pälli b9aa66d5d0 anv: disable preemption for 3DPRIMITIVE during streamout 
This is required by Wa_16013994831.

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20438>
 2022-12-27 15:53:42 +00:00
Tapani Pälli 910f5a18cf intel/genxml: add disable preemption field for gen125 
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20438>
 2022-12-27 15:53:42 +00:00
Lionel Landwerlin afdbed9e9c anv: fix potential integer overflow 
The loop going from 0 to max_draw_count multiplies the value which
could potentially overflow.

Fixes Coverity CID 1517852

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: 3596a8ea7a ("anv: factor out some indirect draw count entry points")
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20436>
 2022-12-27 14:21:44 +00:00
Lionel Landwerlin 2024115b79 intel/ds: add missing generate draws perfetto glue 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: c950fe97a0 ("anv: implement generated (indexed) indirect draws")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/7956
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Tested-by: Vinson Lee <vlee@freedesktop.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20433>
 2022-12-26 14:11:44 +02:00
Lionel Landwerlin c950fe97a0 anv: implement generated (indexed) indirect draws 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Rohan Garg <rohan.garg@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15642>
 2022-12-23 22:52:50 +00:00
Lionel Landwerlin 3596a8ea7a anv: factor out some indirect draw count entry points 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Rohan Garg <rohan.garg@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15642>
 2022-12-23 22:52:50 +00:00
Lionel Landwerlin 61b730f1f4 anv: decouple util function from anv_cmd_buffer 
The issue we're addressing here is that we have 2 batches and the both
grow at different rate. We want to keep doubling the main batch size
as the application writes more and more commands to limit the number
of GEM BOs. But we don't want to have the generation batch size to be
linked to the main batch.

v2: remove gfx7 code

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Rohan Garg <rohan.garg@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15642>
 2022-12-23 22:52:50 +00:00
José Roberto de Souza 3e28c5b9f9 anv: Pass anv_bo as parameter to anv_gem_mmap() 
anv_bo has information that will be needed by a future patch in
anv_gem_mmap(), so here already preparing for that.

Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20423>
 2022-12-23 18:22:29 +00:00
José Roberto de Souza 95ce9664d5 intel/common: Move i915 gem specific code to its own file 
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20423>
 2022-12-23 18:22:29 +00:00
José Roberto de Souza f51bafc368 intel/common: Move i915 engine specific code to its own file 
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20423>
 2022-12-23 18:22:29 +00:00
Väinö Mäkelä 4c986c58b3 intel/blorp: Fix a hang caused by invalid dispatch enables on gfx7 
Because commit b9403b1c47 moved dispatch enable handling away from the
compiler, the drivers must ensure correct dispatch enable values. This
is handled by the intel_set_ps_dispatch_state function.

v2: Fix gfx6 build and use brw_fs_get_dispatch_enables for gfx6 in
crocus
v3: Rebase, use intel_set_ps_dispatch_state, drop gfx6 handling

Fixes: b9403b1c47 ("intel: factor out dispatch PS enabling logic")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20267>
 2022-12-23 10:17:04 +00:00
Tapani Pälli 7db1b94e07 intel/dev: setup 1024 GS urb entries for ADL-N 
v2: apply only for devices with less than 32 EUs (Lionel)

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/7942
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20414>
 2022-12-23 09:51:01 +00:00
Lionel Landwerlin 25608659a0 intel/compiler: mark shader_record_ptr as uniform 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20413>
 2022-12-23 09:22:13 +00:00
Lionel Landwerlin 739a08ad23 anv: handle null push descriptors in deferred optimization 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: b49b18f0 ("anv: reduce BT emissions & surface state writes with push descriptors")
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20410>
 2022-12-22 14:07:21 +00:00
Rohan Garg ad9c0e8cd9 anv: Ensure we clear ANV_PIPE_PSS_STALL_SYNC_BIT on flush 
Add the PSS stall bit to ANV_PIPE_STALL_BITS so that it get's cleared on
flush.

Fixes: f3c62973 ("anv,iris: PSS Stall Sync around color fast clears")

Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20317>
 2022-12-20 10:44:54 +00:00
Chad Versace a5f9e59ce3 anv: Use vma_heap for descriptor pool host allocation 
Pre-patch, anv_descriptor_pool used a free list for host allocations
that never merged adjacent free blocks.  If the pool only allocated
fixed-sized blocks, then this would not be a problem. But the pool
allocations are variable-sized, and this caused over half of the pool's
memory to be consumed by unusable free blocks in some workloads, causing
unnecessary memory footprint.

Replacing the free list with util_vma_heap, which does merge adjacent
free blocks, fixes the memory explosion in the target workload.

Disdavantges of util_vma_heap compared to the free list:
  - The heap calls malloc() when a new hole is created.
  - The heap calls free() when a hole disappears or is merged with an
    adjacent hole.
  - The Vulkan spec expects descriptor set creation/destruction to be
    thread-local lockless in the common case. For workloads that
    create/destroy with high frequency, malloc/free may cause overhead.
    Profiling is needed.

Tested with a ChromeOS internal TensorFlow benchmark, provided by
package 'tensorflow', running with its OpenCL backend on clvk.

  cmdline: benchmark_model --graph=mn2.tflite --use_gpu=true --min_secs=60
  gpu: adl
  memory footprint from start of benchmark:
    before: init=132.691MB max=227.684MB
    after:  init=134.988MB max=134.988MB

Reported-by: Romaric Jodin <rjodin@google.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20289>
 2022-12-16 07:18:38 +00:00
Iván Briano 766508f56a Revert "anv: Refactor anv_pipeline to use the anv_pipeline_type" 
This reverts commit b1126abb38.

This breaks all hell at least on DG2, as there are several cases left
where current_pipeline gets checked against GPGPU to decide what to do,
and the value doesn't match that of ANV_HW_PIPELINE_STATE_COMPUTE.
On top of that, it also misses checking for
ANV_HW_PIPELINE_STATE_RAYTRACING.

Then there's the fact that in some cases, current_pipeline will be
UINT32_MAX, because it's the original undefined state and also used
after executing a secondary command buffer because we are not tracking
on which pipeline did the secondary left us.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/7910
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20349>
 2022-12-16 06:39:32 +00:00
Tapani Pälli 77244e30b6 anv: remove some gen8 specifics handled now in hasvk 
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20342>
 2022-12-16 07:25:30 +02:00
Jordan Justen 5df50292d6 intel/isl: Disable CCS on MTL until B0 (Wa_14017353530) 
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Reviewed-by: Jianxun Zhang <jianxun.zhang@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20322>
 2022-12-15 11:43:00 -08:00