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Author SHA1 Message Date
Georg Lehmann b79950fc1f aco: remove heuristic that restricts VOP2/C with 2 sgprs 
Looking at the stats, the slightly increased code size isn't a problem
compared to the benefits. This also only affects gfx10+, and those generations
aren't throughput limited by 64bit instructions like early gcn.

Foz-DB Navi21:
Totals from 12377 (15.59% of 79395) affected shaders:
MaxWaves: 269323 -> 269857 (+0.20%); split: +0.23%, -0.03%
Instrs: 16505304 -> 16472552 (-0.20%); split: -0.21%, +0.01%
CodeSize: 89815804 -> 90130344 (+0.35%); split: -0.02%, +0.37%
VGPRs: 661160 -> 658640 (-0.38%); split: -0.40%, +0.02%
SpillSGPRs: 3032 -> 3049 (+0.56%)
SpillVGPRs: 826 -> 796 (-3.63%)
Latency: 145800231 -> 145818568 (+0.01%); split: -0.14%, +0.15%
InvThroughput: 39026010 -> 38892467 (-0.34%); split: -0.36%, +0.02%
VClause: 325693 -> 325992 (+0.09%); split: -0.12%, +0.21%
SClause: 497938 -> 497208 (-0.15%); split: -0.23%, +0.08%
Copies: 1239036 -> 1204045 (-2.82%); split: -2.90%, +0.07%
Branches: 462952 -> 462934 (-0.00%); split: -0.01%, +0.00%
PreSGPRs: 586066 -> 587558 (+0.25%)
PreVGPRs: 550024 -> 547736 (-0.42%)
VALU: 11147608 -> 11114528 (-0.30%); split: -0.31%, +0.01%
SALU: 2105546 -> 2105131 (-0.02%); split: -0.03%, +0.01%
VMEM: 575983 -> 575923 (-0.01%)

Foz-DB Navi31:
Totals from 11544 (14.54% of 79395) affected shaders:
MaxWaves: 319612 -> 319804 (+0.06%)
Instrs: 17563158 -> 17527341 (-0.20%); split: -0.22%, +0.02%
CodeSize: 92366832 -> 92626280 (+0.28%); split: -0.03%, +0.31%
VGPRs: 667620 -> 665484 (-0.32%); split: -0.33%, +0.01%
SpillSGPRs: 3418 -> 3434 (+0.47%)
SpillVGPRs: 896 -> 858 (-4.24%)
Scratch: 4738048 -> 4736512 (-0.03%)
Latency: 141366653 -> 141399756 (+0.02%); split: -0.10%, +0.12%
InvThroughput: 26213994 -> 26165751 (-0.18%); split: -0.21%, +0.03%
VClause: 307956 -> 308124 (+0.05%); split: -0.12%, +0.18%
SClause: 477816 -> 477326 (-0.10%); split: -0.18%, +0.08%
Copies: 1161148 -> 1129386 (-2.74%); split: -2.81%, +0.08%
Branches: 411509 -> 411506 (-0.00%); split: -0.00%, +0.00%
PreSGPRs: 531354 -> 535027 (+0.69%)
PreVGPRs: 525201 -> 521861 (-0.64%)
VALU: 10360363 -> 10330274 (-0.29%); split: -0.30%, +0.01%
SALU: 1778044 -> 1777585 (-0.03%); split: -0.04%, +0.01%
VMEM: 551379 -> 551303 (-0.01%)
VOPD: 3539 -> 3471 (-1.92%); split: +0.14%, -2.06%

Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31804>
 2024-10-24 17:44:13 +00:00
Georg Lehmann 54fa55a3f7 radv: don't use v_mqsad_u32_u8 on gfx7 
According to tests on hawaii, v_mqsad_u32_u8 always uses saturating accumulation
while v_msad_u8 truncates. GFX8+ can control this with the VOP3 clamp bit,
on older hardware that's not supported.

We want truncation for the NIR opcode.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/12062
Fixes: c3c138b10f ("radv: optimize msad_4x8 to mqsad_4x8")
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31809>
 2024-10-24 17:20:56 +00:00
Eric Engestrom a85ed2a28f lavapipe/ci: document regression in the commit range 765d1c47...366f63fd 
There's a cts uprev in one of these commits, so it's possible they're all just new tests.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31825>
 2024-10-24 16:50:44 +00:00
Eric Engestrom 150fd992b6 lavapipe/ci: skip builtin ray query tests that take too long and time out 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31825>
 2024-10-24 16:50:44 +00:00
Eric Engestrom 4724bbe7a7 lavapipe/ci: group & sort skips 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31825>
 2024-10-24 16:50:44 +00:00
Eric Engestrom 6d3e1ab56d lavapipe/ci: group & sort fails 
They were in a completely random order, making it hard to see anything.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31825>
 2024-10-24 16:50:44 +00:00
Eric Engestrom 831eab2375 nvk/ci: add flakes seen recently 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31825>
 2024-10-24 16:50:44 +00:00
Eric Engestrom dff8ece33f turnip/ci: add more dEQP-VK.renderpass2.fragment_density_map.* flakes seen recently 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31825>
 2024-10-24 16:50:44 +00:00
Eric Engestrom 1c61e5c40f zink+nvk/ci: add flakes seen recently 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31825>
 2024-10-24 16:50:44 +00:00
Eric Engestrom cd912582bf zink+nvk/ci: drop duplicate flakes lines 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31825>
 2024-10-24 16:50:44 +00:00
Eric Engestrom b6bd7522f1 all-drivers/ci: drop duplicate flakes lines 
Done programmatically, not manually, so there shouldn't be any incorrect
removal.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31825>
 2024-10-24 16:50:44 +00:00
Eric Engestrom 454d9dbbd0 zink+nvk/ci: document ext_egl_image_storage regression in c06a55fd...2fb4aed9 (likely !31585) 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31825>
 2024-10-24 16:50:44 +00:00
Eric Engestrom 654683143b nvk/ci: add back a crash that was mistakenly removed from the expectations 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31825>
 2024-10-24 16:50:44 +00:00
Eric Engestrom bf0c24da2d docs: update link to perf wiki 
https://perf.wiki.kernel.org/ is now a permanent http redirect to
https://perfwiki.github.io/, which itself is an html redirect to
https://perfwiki.github.io/main/, but let's just link to the root and
let the second redirection be a detail on their side.

Since the second redirection is not an http redirection, it won't light
up the linkcheck, so we don't have to add an equivalent line to what was
previously there.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31824>
 2024-10-24 16:42:41 +00:00
Rhys Perry 4579586c66 aco/tests: add tests for VALUReadSGPRHazard 
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30478>
 2024-10-24 16:08:08 +00:00
Rhys Perry 47e0f468cf aco: workaround VALUReadSGPRHazard 
fossil-db (gfx1200):
Totals from 65112 (82.01% of 79395) affected shaders:
Instrs: 41732906 -> 42987198 (+3.01%); split: -0.00%, +3.01%
CodeSize: 222451964 -> 226942644 (+2.02%); split: -0.01%, +2.03%
Latency: 290411063 -> 290944688 (+0.18%); split: -0.00%, +0.18%
InvThroughput: 45854913 -> 45910275 (+0.12%); split: -0.00%, +0.12%

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30478>
 2024-10-24 16:08:07 +00:00
Rhys Perry 9ab0c4b047 aco: minor CounterMap::operator== fix 
I don't think this matters for how we use CounterMap::operator==.

The BITSET_TEST() was unnecessary because of the BITSET_EQUAL above.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30478>
 2024-10-24 16:08:07 +00:00
Rhys Perry f5b871f825 aco: split CounterMap off from VGPRCounterMap 
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30478>
 2024-10-24 16:08:07 +00:00
Rhys Perry d312220c2d aco,radv,radeonsi: add aco_shader_info::ps::has_prolog 
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30478>
 2024-10-24 16:08:07 +00:00
Erik Faye-Lund 23c34f89fc panvk: fix broken wsi 
We don't need to bend over backwards to try to repair the consequences
of something that happened earlier when we can just prevent that from
happening in the first palce instead.

While we're at it, also move the cmd_dispatch initialization into the
conditional block, because that's only used by the secondary-buffer
emulation code.

This fixes WSI, because there's more differences than just secondary
command buffers between the device-level dispatch-table and the
cmd_dispatch table.

Fixes: c2299b6642 ("panvk/csf: Implement vkCmdExecuteCommands")
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31819>
 2024-10-24 15:33:59 +00:00
Connor Abbott 048afdd438 tu: Don't invalidate CS state for 3D blits 
We don't dirty the CS state, so if a 3D blit comes between binding a
compute pipeline and executing a dispatch then we won't re-emit the
pipeline and invalidating CS state causes immediates emitted via
CP_LOAD_STATE to disappear. Fixes
dEQP-VK.binding_model.descriptor_buffer.ycbcr_sampler.compute_comp.

Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31764>
 2024-10-24 14:56:04 +00:00
Connor Abbott 3e3c1b042e tu: Implement VK_PIPELINE_CREATE_2_VIEW_INDEX_FROM_DEVICE_INDEX_BIT_KHR 
This was missed because the tests for it were broken. An upcoming CTS
fix will make the tests actually useful, and with this change they pass.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31764>
 2024-10-24 14:56:04 +00:00
Connor Abbott 3c8190e8b2 freedreno: Add compute constlen quirk for X1-85 
This GPU seems to have half the compute constlen of other a7xx GPUs,
because there are sporadic hangs in dEQP-VK.robustness.robustness2.* and
other tests unless we limit the constlen. This does *not* happen on
SM8550-HDK, so it does seem to be specific to the GPU in x1e laptops.

Fixes: b0d22461b9 ("freedreno: Enable the X1-85")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31764>
 2024-10-24 14:56:03 +00:00
Samuel Pitoiset 605d4dd42a radv: do not use MRT counters for images created for db capture&replay 
Setting the surface index is optimal for performance in case of
multiple MRTs because addrlib rotates tiles differently.

But this should be disabled when the image is used for descriptor
buffers capture&replay because the descriptor isn't immutable
(ie. tile_swizzle can be different).

This fixes dEQP-VK.binding_model.descriptor_buffer.capture_replay.*
on some GPUs where tile_swizzle is non-zero.

Fixes: 3b57a35ece ("radv: Enable descriptorBufferCaptureReplay.")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31818>
 2024-10-24 13:53:20 +00:00
David Rosca 35eb12e2fd frontends/va: Evict unused surfaces from encode DPB 
Application should send the full DPB state in each pic to keep
the references alive. Ideally the surfaces would be evicted immediately,
but unfortunately this breaks some applications. Add evict flag and
only evict surfaces if not present in reference frames array for two
consecutive frames.
DPB buffers are not destroyed upon eviction, but instead they are kept
around and reused next time a new surface is added to DPB.

Fixes: cc14724d73 ("frontends/va: Implement DPB management for H264/5 encode")
Reviewed-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31741>
 2024-10-24 12:36:37 +00:00
David Rosca 33c6491244 pipe: Fix video enc max DPB size for H264 
H264 have 16 as maximum DPB size by spec (A.3.1. f) MaxDpbFrames).
For encode we need one more slot for current recon, so use max size + 1.

Fixes: cc14724d73 ("frontends/va: Implement DPB management for H264/5 encode")
Reviewed-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31741>
 2024-10-24 12:36:37 +00:00
Yao Zi 5ffc5ba8ef panvk: Link with --build-id explicitly 
panvk provides driver UUID generated from build id of the dynamic
library, but ld_args_build_id isn't used during linking. This leads to
broken drivers when building mesa with a toolchain defaults to
--no-build-id. Let's specify the flag explicitly.

Fixes: 8ea2931ed1 ("panvk: Generate proper device and driver UUIDs")
Signed-off-by: Yao Zi <ziyao@disroot.org>
Reviewed-by: Mary Guillemard <mary.guillemard@collabora.com>
Acked-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31654>
 2024-10-24 12:09:16 +00:00
Rhys Perry d227968201 ac/llvm: cast to integer after derivative intrinsics 
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Fixes: daa97bb41a ("amd: switch to derivative intrinsics")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31788>
 2024-10-24 11:23:07 +00:00
Danylo Piliaiev 3209a97c5c util/vma: Fix util_vma_heap_get_max_free_continuous_size calculation 
It was based on misunderstanding of how holes are sorted, they are
sorted by address and not by size.

Fixes: df3ba95a24
("util/vma: Add function to get max continuous free size")

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31722>
 2024-10-24 10:50:08 +00:00
Daniel Schürmann 87cb42f953 treewide: don't lower to LCSSA before calling nir_divergence_analysis() 
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30787>
 2024-10-24 10:06:17 +00:00
Daniel Schürmann 95ed72922e nir/divergence: Don't assume that LCSSA phis are not loop-invariant 
Since we check for loop-invariance, we don't have to unconditionally
flag LCSSA phis as divergent in presence of divergent breaks.
This ensures consistency, with or without LCSSA form.

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30787>
 2024-10-24 10:06:17 +00:00
Daniel Schürmann c5f142a695 nir/divergence: skip expensive nir_src_is_divergent() check in most cases 
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30787>
 2024-10-24 10:06:17 +00:00
Daniel Schürmann 0eff03d385 nir/divergence: calculate divergence without requiring LCSSA form 
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30787>
 2024-10-24 10:06:17 +00:00
Daniel Schürmann d34d2f8fa8 nir: consider loop invariance in nir_src_is_divergent() 
By doing so, this function does not require LCSSA form anymore
in order to provide correct results.

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30787>
 2024-10-24 10:06:17 +00:00
Daniel Schürmann 1a55d6c23b nir/divergence: Introduce and set nir_def::loop_invariant 
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30787>
 2024-10-24 10:06:17 +00:00
Daniel Schürmann c0b3d7a916 nir/divergence: require nir_metadata_block_index 
This allows for fast checks whether some value is defined inside a loop.

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30787>
 2024-10-24 10:06:17 +00:00
Daniel Schürmann 8d1abd4996 treewide: use nir_src_is_divergent() rather than checking the divergence of the SSA 
Without LCSSA, divergence between src and def might differ.

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30787>
 2024-10-24 10:06:17 +00:00
Daniel Schürmann c8348139fd nir: change signature of nir_src_is_divergent() 
Now, it takes nir_src * instead of nir_src.
Also move the implementation to nir_divergence_analysis.c.

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30787>
 2024-10-24 10:06:17 +00:00
Daniel Schürmann 421b42637d nir: remove nir_update_instr_divergence() 
This function has obscure limitations.

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30787>
 2024-10-24 10:06:17 +00:00
Daniel Schürmann ce0a3fe645 nir/opt_uniform_atomics: don't preserve divergence information 
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30787>
 2024-10-24 10:06:17 +00:00
Daniel Schürmann c25c63ebc0 nir/divergence: separately indicate whether loops have divergent continues or breaks 
bool nir_loop_is_divergent(nir_loop *)
 replaces the previous loop->divergent indicator.

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30787>
 2024-10-24 10:06:17 +00:00
Jordan Justen a4c5bfd34c intel/dev: Use hwconfig for urb min/max entry values 
Backport-to: 24.2
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31692>
 2024-10-24 09:21:56 +00:00
Jordan Justen 7b86da0ccd intel/dev: Allow specifying a version when to always use hwconfig 
Backport-to: 24.2
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31692>
 2024-10-24 09:21:56 +00:00
Jordan Justen a71702d342 intel/dev: Simplify DEVINFO_HWCONFIG_KV by adding should_apply_hwconfig_item() 
Backport-to: 24.2
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31692>
 2024-10-24 09:21:56 +00:00
Jordan Justen b4df9658f5 intel/dev: Rework DEVINFO_HWCONFIG; add DEVINFO_HWCONFIG_KV macro 
Backport-to: 24.2
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31692>
 2024-10-24 09:21:56 +00:00
Vignesh Raman ce98715566 ci/crosvm: Use default value for CROSVM_GALLIUM_DRIVER 
Use a default value for CROSVM_GALLIUM_DRIVER. This change
ensures that if the variable is unset, it defaults to an
empty string. This prevents unbound variable errors with
set -u in the case of drm-ci.

Signed-off-by: Vignesh Raman <vignesh.raman@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31814>
 2024-10-24 08:46:54 +00:00
Stéphane Cerveau ac2b7d07e4 anv: check that inline query pool is VK_NULL_HANDLE 
Reviewed-by: Hyunjun Ko <zzoon@igalia.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: Stéphane Cerveau <scerveau@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31765>
 2024-10-24 08:17:11 +00:00
Stéphane Cerveau aaa5770d4b anv: inline query for vulkan video encode 
Follow up of the work performed in decode to
support inline query.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Hyunjun Ko <zzoon@igalia.com>
Signed-off-by: Stéphane Cerveau <scerveau@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31765>
 2024-10-24 08:17:11 +00:00
Samuel Pitoiset be81c8b8db radv: fix initializing the HTILE buffer on transfer queue 
When only of the depth/stencil aspects is used, RADV dispatches a
compute shader to initialize the HTILE buffer. But dispatching on SDMA
just hangs and the only way to initialize the HTILE buffer is to clear
both aspects using a memory fill operation.

Cc: mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31803>
 2024-10-24 06:25:18 +00:00
Tapani Pälli dcb88ea4ab anv/iris: add note about Wa_18039438632 for RT flush after SBA 
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31801>
 2024-10-24 04:29:56 +00:00