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Author SHA1 Message Date
José Roberto de Souza 7295e09b53 intel/dev: Drop coherency from intel_device_info_pat_entry 
It is not used in run-time so we can drop from the struct.
It might have value as PAT entries documentation but that will be done
in the next patch.

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Jianxun Zhang <jianxun.zhang@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29950>
 2024-07-17 17:41:32 +00:00
José Roberto de Souza fa1129540a intel/dev: Add documentation about intel_device_info_pat_entry::mmap 
My initial understating was that L3_CACHE_POLICY would be the CPU
caching mode but that has nothing to do with CPU caching, it is the
GPU caching mode.

Due this miss understating we were using a not optimal PAT index that
will be fixed in the next patches, so to avoid such issues in future
adding comments to intel_device_info_pat_entry struct.

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Jianxun Zhang <jianxun.zhang@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29950>
 2024-07-17 17:41:32 +00:00
José Roberto de Souza 4173e0f910 intel/dev: Drop DG1 PAT entries 
It inherents that table from TGL.

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Jianxun Zhang <jianxun.zhang@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29950>
 2024-07-17 17:41:32 +00:00
José Roberto de Souza 178950bf9b anv: Fix return of PAT index for compressed bos for discrete GPUs 
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Jianxun Zhang <jianxun.zhang@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29950>
 2024-07-17 17:41:32 +00:00
Eric Engestrom ad96a99385 docs: add sha256sum for 24.1.4 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30226>
 2024-07-17 17:34:13 +00:00
Eric Engestrom 096548bbe9 docs: update calendar for 24.1.4 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30226>
 2024-07-17 17:34:13 +00:00
Eric Engestrom cc078c2dcf docs: add release notes for 24.1.4 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30226>
 2024-07-17 17:34:13 +00:00
Samuel Pitoiset 619bcd3b5c radv: allow to capture with RGP on GFX11_5 
It works fine.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30225>
 2024-07-17 16:25:19 +00:00
Samuel Pitoiset e2882ea3e2 ac/rgp: assume GFX11_5 use the same SQTT/RGP versions as GFX11 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30225>
 2024-07-17 16:25:19 +00:00
Samuel Pitoiset 664a31bcd1 radv: disable SPM trace on GFX11_5 
SPM needs performance counters and they aren't exposed yet.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30225>
 2024-07-17 16:25:19 +00:00
Samuel Pitoiset 057c4e3786 radv: expose BufferFloat32AtomicMinMax on GFX11_5 
This is supported like GFX11.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30225>
 2024-07-17 16:25:19 +00:00
Samuel Pitoiset d2ae0c9ef8 radv: fix programming DB_RENDER_CONTROL for NULL depth/stencil on GFX11_5 
It should be programmed like GFX11.

Cc: mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30225>
 2024-07-17 16:25:19 +00:00
Samuel Pitoiset 1c5779250b radv: do not expose ImageFloat32AtomicMinMax on GFX11_5 
These opcodes aren't supported on GFX11-11.5.

Cc: mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30225>
 2024-07-17 16:25:19 +00:00
Georg Lehmann eff0998064 radv: use radv_nir_opt_tid_function to create inverse_ballot 
Foz-DB Navi21:
Totals from 542 (0.68% of 79395) affected shaders:
Instrs: 617316 -> 616259 (-0.17%); split: -0.19%, +0.02%
CodeSize: 3347852 -> 3320040 (-0.83%); split: -0.85%, +0.02%
VGPRs: 21864 -> 21824 (-0.18%); split: -0.29%, +0.11%
SpillSGPRs: 207 -> 199 (-3.86%)
Latency: 4900847 -> 4895665 (-0.11%); split: -0.11%, +0.01%
InvThroughput: 860278 -> 857272 (-0.35%); split: -0.35%, +0.00%
SClause: 21251 -> 21169 (-0.39%); split: -0.40%, +0.01%
Copies: 57759 -> 58881 (+1.94%); split: -0.06%, +2.00%
Branches: 20854 -> 20365 (-2.34%); split: -2.36%, +0.01%
PreSGPRs: 20785 -> 20774 (-0.05%)
PreVGPRs: 17309 -> 17212 (-0.56%)
VALU: 379885 -> 378180 (-0.45%); split: -0.45%, +0.00%
SALU: 87522 -> 88664 (+1.30%); split: -0.02%, +1.32%

Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24650>
 2024-07-17 15:04:38 +00:00
Georg Lehmann 39de178656 radv: use radv_nir_opt_tid_function for shuffles 
The main motivation were open coded clustered inclusive scans
and clustered broadcasts in the gdeflate decompression shader used by
DirectStorage.

Foz-DB Navi21 (only the_last_of_us_part1 is affected):
Totals from 8 (0.01% of 79395) affected shaders:
Instrs: 6230 -> 5438 (-12.71%)
CodeSize: 33376 -> 29148 (-12.67%)
Latency: 77017 -> 72917 (-5.32%)
InvThroughput: 10190 -> 9280 (-8.93%)
Copies: 566 -> 569 (+0.53%)
PreSGPRs: 528 -> 524 (-0.76%)
PreVGPRs: 232 -> 230 (-0.86%)
VALU: 2889 -> 2616 (-9.45%)
SALU: 1748 -> 1491 (-14.70%); split: -14.82%, +0.11%

Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24650>
 2024-07-17 15:04:38 +00:00
Georg Lehmann ca88783318 radv/nir: add a pass to optimize shuffle/booleans dependent only on tid/consts 
This pass uses constant folding to determine which invocation is read by shuffle
for each invocation. Then, it detects patterns in the result and uses more
a specialized intrinsic if possible.

For booleans it creates inverse_ballot.

Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24650>
 2024-07-17 15:04:38 +00:00
Georg Lehmann 2d3f536174 aco,nir: add dpp16_shift_amd intrinsic 
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24650>
 2024-07-17 15:04:38 +00:00
Faith Ekstrand 1f430b1111 nak/nir: Make interpolate_at_sample more efficient 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30218>
 2024-07-17 13:38:24 +00:00
Faith Ekstrand 24d5acf052 nak/nir: Use prmt for barycentric offset lowering 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30218>
 2024-07-17 13:38:24 +00:00
Faith Ekstrand fffbd3ff2b nak/nir: Use prmt in texture lowering 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30218>
 2024-07-17 13:38:24 +00:00
Faith Ekstrand bbccbd8d50 nir,nak: Add a nir_op_prmt_nv 
We have this in hardware since forever and it's really useful.  May as
well add it to NIR so we can use it in various lowerings.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30218>
 2024-07-17 13:38:24 +00:00
Faith Ekstrand 3619ec9630 nak: Don't print the destination of OpIpa twice 
While we're here, also implement Display for InterpFreq and InterpLoc
and simplify printing a bit.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30218>
 2024-07-17 13:38:24 +00:00
Faith Ekstrand ef88597ebb nak/copy_prop: Ignore the top 16 bits of OpPrmt::sel 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30218>
 2024-07-17 13:38:24 +00:00
Faith Ekstrand f949c00170 nak/copy_prop: Propagate OpSel with a selector of SrcRef::Zero 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30218>
 2024-07-17 13:38:24 +00:00
Faith Ekstrand cc33cafcac nak/nir: Use an indirect load for sample locations 
A single ldc is probably more efficient than a 64-bit load and the pile
of math we were generating before.  The only reason for the old method
was that it let us avoid indirect cbuf loads because we didn't support
them for a while.  Now that we can support all cbuf loads, we can just
do an indirect 1B load and call it good.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30218>
 2024-07-17 13:38:24 +00:00
Mike Blumenkrantz f673e2bf68 winsys/radeon: switch to rendernode when card node doesn't work 
initializing the winsys from a /dev/dri/cardX node (as discovered by
gbm) doesn't work, as the kernel abi expects a render node

thus, the winsys needs to open the card's rendernode and use that
everywhere except when importing buffers, where it has to explicitly
export from the card node and import to the rendernode

Acked-by: Daniel Stone <daniels@collabora.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30224>
 2024-07-17 13:20:48 +00:00
Mike Blumenkrantz 216ff9591b winsys/radeon: wrap fd access with util function 
no functional changes

Acked-by: Daniel Stone <daniels@collabora.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30224>
 2024-07-17 13:20:48 +00:00
Mike Blumenkrantz ec2451fcb3 winsys/radeon: take the full winsys struct in radeon_get_drm_value() 
Acked-by: Daniel Stone <daniels@collabora.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30224>
 2024-07-17 13:20:48 +00:00
Mary Guillemard 10d9bc3a2c panfrost: Fetch available system memory 
This reproduces panvk logic of showing how much memory is available
while taking into account the address space limits we have.

Signed-off-by: Mary Guillemard <mary.guillemard@collabora.com>
Reviewed by: Eric R. Smith <eric.smith@collabora.com>

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30088>
 2024-07-17 12:04:11 +00:00
Mary Guillemard 02e38664f3 panfrost: Increase address space to 48-bit 
Valhall can allow up to 48-bit of address space, we should reflect this
here to allow more memory to be mapped in the same address space when
possible.

Signed-off-by: Mary Guillemard <mary.guillemard@collabora.com>
Reviewed by: Eric R. Smith <eric.smith@collabora.com>

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30088>
 2024-07-17 12:04:11 +00:00
Mary Guillemard 04685e732e panfrost: Do not recreate bo if already mapped 
Signed-off-by: Mary Guillemard <mary.guillemard@collabora.com>
Reviewed by: Eric R. Smith <eric.smith@collabora.com>

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30088>
 2024-07-17 12:04:11 +00:00
Mary Guillemard 3f2793ee10 panfrost: Rewrite set_global_binding to make resources truly global 
Before this, CL buffers would not be attached to subsequent batches.

This fix spurious fails when running OpenCL CTS test_basic astype and
likely others.

Signed-off-by: Mary Guillemard <mary.guillemard@collabora.com>
Reviewed by: Eric R. Smith <eric.smith@collabora.com>

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30088>
 2024-07-17 12:04:11 +00:00
Mary Guillemard 801922cbe6 bi: Implement basic 8-bit vec support 
Not the most efficient approach but functional.

Signed-off-by: Mary Guillemard <mary.guillemard@collabora.com>
Acked-by: Rebecca Mckeever <rebecca.mckeever@collabora.com>
Reviewed by: Eric R. Smith <eric.smith@collabora.com>

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30088>
 2024-07-17 12:04:11 +00:00
Mary Guillemard 368100d71c bi: Enable lower_pack pass in compiler 
Required for OpenCL

Signed-off-by: Mary Guillemard <mary.guillemard@collabora.com>
Reviewed by: Eric R. Smith <eric.smith@collabora.com>

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30088>
 2024-07-17 12:04:11 +00:00
Mary Guillemard 5420b73925 bi: Lower pack_32_4x8_split and pack_32_2x16_split in algebraic 
Required for OpenCL.

Signed-off-by: Mary Guillemard <mary.guillemard@collabora.com>
Reviewed by: Eric R. Smith <eric.smith@collabora.com>

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30088>
 2024-07-17 12:04:10 +00:00
Mary Guillemard 32ef369322 bi: Enable lower_pack_64_4x16 
Required for OpenCL.

Signed-off-by: Mary Guillemard <mary.guillemard@collabora.com>
Reviewed by: Eric R. Smith <eric.smith@collabora.com>

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30088>
 2024-07-17 12:04:10 +00:00
Mary Guillemard 02cea97629 bi: Clean up mem_access_size_align_cb 
Also ensure that we never emit vector with more than 4 components.

Signed-off-by: Mary Guillemard <mary.guillemard@collabora.com>
Reviewed-by: Eric R. Smith <eric.smith@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30088>
 2024-07-17 12:04:10 +00:00
Mary Guillemard 660218529c rusticl: Add panthor when panfrost is present in RUSTICL_ENABLE 
Signed-off-by: Mary Guillemard <mary.guillemard@collabora.com>
Reviewed by: Eric R. Smith <eric.smith@collabora.com>

Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30088>
 2024-07-17 12:04:10 +00:00
Eric Engestrom e565873911 features.txt: specify that GL_ARB_depth_clamp is only supported on v3d/vc7+ 
Fixes: cbd3927445 ("v3d: expose ARB_depth_clamp in V3D 7.x")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30185>
 2024-07-17 11:58:21 +00:00
Eric Engestrom 4e9c16b035 features.txt: specify that VK_EXT_depth_clip_enable is only supported on v3dv/vc7+ 
Fixes: 16f6f50ce4 ("v3dv: expose VK_EXT_depth_clip_enable")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30185>
 2024-07-17 11:58:21 +00:00
Eric Engestrom f5a93fa83b features.txt: specify that VK_EXT_depth_clamp_zero_one is only supported on v3dv/vc7+ 
Fixes: f8623ea7da ("v3dv: adversise VK_EXT_depth_clamp_zero_one")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30185>
 2024-07-17 11:58:21 +00:00
Sergi Blanch Torne e6de8e2533 ci: fix run_n_monitor single execution 
When there is a single job as a target and, when it is triggered, it takes
more than one loop time in pending status, it confuses the script to fall in
a wrong return of the pipeline monitoring.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/11517

Signed-off-by: Sergi Blanch Torne <sergi.blanch.torne@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30219>
 2024-07-17 11:25:50 +00:00
Marek Olšák 15461dc62f mesa: switch ID allocation to util_idalloc_sparse to reduce virtual memory usage 
If the max ID was allocated, it caused virtual memory usage to increase
to 512 MB. This commit reduced it to 512 KB.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/10968

Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30106>
 2024-07-17 10:29:12 +00:00
Marek Olšák d4085aaf56 util: add util_idalloc_sparse, solving the excessive virtual memory usage 
The code comment in the header file describes how it works.

Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30106>
 2024-07-17 10:29:12 +00:00
Marek Olšák ace7c32333 util: don't use variable names that can appear in args of idalloc foreach macros 
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30106>
 2024-07-17 10:29:12 +00:00
Marek Olšák 287ed620d0 util: make util_idalloc_exists private 
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30106>
 2024-07-17 10:29:12 +00:00
Faith Ekstrand 2d260314f1 nvk: Use the page size queried from NVKMD 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30138>
 2024-07-17 08:17:57 +00:00
Faith Ekstrand 68c06558be nvk: Drop the sparse alignment back down to 4096 
nouveau uses the OS page size which is almost always 4096.  The next
patch will make this properly queried but this version is back-portable.

Fixes: 58181b7bbc ("nvk: Bump the sparse alignment requirement on buffers to 64K")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30138>
 2024-07-17 08:17:57 +00:00
Faith Ekstrand bccb9fe091 nvk/nvkmd: nouveau uses the OS page size 
It's the same, regardless of whether the memory comes from VRAM or
system RAM.

Fixes: 7f45d20d2b ("nvk/nvkmd: Be more specific about memory alignments")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30138>
 2024-07-17 08:17:56 +00:00
Iago Toral Quiroga 78c00fbc2c v3d: rename job->clear to job->clear_tlb 
This is more specific as to the type of clear it represents.

Reviewed-by: Jose Maria Casanova Crespo <jmcasanova@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30205>
 2024-07-17 06:03:12 +00:00