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Author SHA1 Message Date
Alyssa Rosenzweig 3cfe2fc1b1 pan/mdg: Identify scalar integer mods 
Symmetric with vector mods, except for normal which is packed as
sign-extend. (flag 2 never seen in the wild)

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5151>
 2020-05-21 17:49:14 +00:00
Alyssa Rosenzweig d4a42a78d8 pan/mdg: Use type to determine triviality of a move 
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5151>
 2020-05-21 17:49:14 +00:00
Alyssa Rosenzweig df3d932bb4 pan/mdg: Use src_types to determine size in scheduling 
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5151>
 2020-05-21 17:49:14 +00:00
Alyssa Rosenzweig 95dd478ed3 pan/mdg: Add abs/neg/shift modifiers to IR 
Rather than twiddling them into the ALU packed field.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5151>
 2020-05-21 17:49:14 +00:00
Alyssa Rosenzweig 31e13956e1 pan/mdg: Explain ld/st sign/zero extension 
Now we know why there are duplicates :-)

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5151>
 2020-05-21 17:49:14 +00:00
Alyssa Rosenzweig dbcae7c667 pan/mdg: Respect !32-bit sizes in RA 
So we can take advantage of mediump.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5151>
 2020-05-21 17:49:14 +00:00
Alyssa Rosenzweig 8c012c8f8b pan/mdg: Handle dest up/lower correctly with swizzles 
During emit time.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5151>
 2020-05-21 17:49:14 +00:00
Alyssa Rosenzweig 8084fc3b66 pan/mdg: Include more types 
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5151>
 2020-05-21 17:49:14 +00:00
Alyssa Rosenzweig e9a4bd90a8 pan/mdg: Remove mir_get_alu_src 
Unused.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5151>
 2020-05-21 17:49:14 +00:00
Alyssa Rosenzweig 9915bb2c40 pan/mdg: Remove mir_*size routines 
We'd rather use the actual type information than inferring modes all
over the place.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5151>
 2020-05-21 17:49:13 +00:00
Alyssa Rosenzweig 40e9bee714 pan/mdg: Fix constant combining crash 
We need to round up.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5151>
 2020-05-21 17:49:13 +00:00
Alyssa Rosenzweig eb28a3669b pan/mdg: Handle comparisons in fp16 path 
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5151>
 2020-05-21 17:49:13 +00:00
Samuel Pitoiset 2d4493ee11 aco: sign-extend the input and identity for 8-bit subgroup operations 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4494>
 2020-05-21 15:06:48 +00:00
Samuel Pitoiset c76595aec2 aco: use a temporary SGPR for 8-bit/16-bit literal reduction identities 
Otherwise, the compiler overwrites s0 which contains the exec mask.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4494>
 2020-05-21 15:06:48 +00:00
Samuel Pitoiset b3c87c52ea aco: implement 8-bit/16-bit nir_intrinsic_quad_* 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4494>
 2020-05-21 15:06:48 +00:00
Samuel Pitoiset dfa62d97a0 aco: implement 8-bit/16-bit nir_intrinsic_{shuffle,_read_invocation} 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4494>
 2020-05-21 15:06:48 +00:00
Samuel Pitoiset f03e56eaf0 aco: implement 8-bit/16-bit nir_intrinsic_read_first_invocation 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4494>
 2020-05-21 15:06:48 +00:00
Samuel Pitoiset af7e2c6133 aco: validate 8-bit/16-bit VGPR operands for readfirstlane/readlane/writelane 
I would expect it to just work as intended and other solutions,
like v_and_b32 to make sure the upper bits are 0, might have some
overhead.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4494>
 2020-05-21 15:06:48 +00:00
Samuel Pitoiset 86e2b03e3f aco: implement 8-bit/16-bit reductions 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4494>
 2020-05-21 15:06:48 +00:00
Samuel Pitoiset cc79945b21 aco: declare 8-bit/16-bit reduce operations 
The 8-bit float variants are only for consistency but are unused.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4494>
 2020-05-21 15:06:48 +00:00
Eric Engestrom bf97150d45 no_extern_c.h: fix typo in comment 
Signed-off-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5145>
 2020-05-21 14:23:41 +00:00
Erik Faye-Lund 089b0310ef docs: fix broken release-calendar 
This also removed the branch-row, which is needed to keep things sane.

Fixes: 34718070ef ("docs: update calendar for 20.1.0-rc4")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5143>
 2020-05-21 14:15:24 +00:00
Rhys Perry 40ed7fcc0b aco: fix typo in insert_waitcnt's kill() 
No shader-db changes

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/3004
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5126>
 2020-05-21 13:01:41 +00:00
Daniel Schürmann 51f4b22fee aco: don't allow unaligned subdword accesses on GFX6/7 
There are no SDWA instructions which means that only
full registers can be accessed.

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5070>
 2020-05-21 12:07:40 +00:00
Daniel Schürmann ae390755fe aco: fix corner case in register allocation 
We mark dead operands in the register file when searching for
a register for a definition. Only do so, if this space has not
yet been taken by a different definition.

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5070>
 2020-05-21 12:07:40 +00:00
Daniel Schürmann acec00eae0 aco: don't move create_vector subdword operands to unsupported register offsets 
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5070>
 2020-05-21 12:07:40 +00:00
Daniel Schürmann 5201985332 aco: restrict copying of create_vector operands to GFX9+ 
This improves code size for Polaris and earlier due to less register swapping

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5070>
 2020-05-21 12:07:40 +00:00
Pierre Moreau 8635c28a92 clover: Address unnecessary copy warnings 
Signed-off-by: Pierre Moreau <dev@pmoreau.org>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4943>
 2020-05-21 10:58:05 +00:00
Pierre Moreau 15a27ed73b clover/api: Address missing braces for subobj init 
Signed-off-by: Pierre Moreau <dev@pmoreau.org>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4943>
 2020-05-21 10:58:05 +00:00
Danylo Piliaiev 5500a2b7fc meson: Disable GCC's dead store elimination for memory zeroing custom new 
Some classes use custom new operator which zeroes memory, however gcc does
aggressive dead-store elimination which threats all writes to the memory
before the constructor as "dead stores".

For now we disable this optimization.

The new operators in question are declared via:
 DECLARE_RZALLOC_CXX_OPERATORS
 DECLARE_LINEAR_ZALLOC_CXX_OPERATORS

The issue was found with lto builds, however there is no guarantee that
it didn't happen with ordinary ones.

CC: <mesa-stable@lists.freedesktop.org>
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/2977
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/1358
Signed-off-by: Danylo Piliaiev <danylo.piliaiev@globallogic.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5104>
 2020-05-21 08:54:30 +00:00
Samuel Pitoiset a3045cbc97 radv/winsys: remove useless free in radv_amdgpu_create_bo_list() 
free(NULL) is fine but let's remove it.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/3008
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5131>
 2020-05-21 08:09:18 +00:00
Samuel Pitoiset 57a4837f6b radv: fix duplicated expression in ac_setup_rings() 
Probably a search&replace mistake when that common struct was
introduced.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/3006
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5130>
 2020-05-21 07:51:55 +00:00
Samuel Pitoiset ef042ae7c3 radv: fix missing break in radv_GetPhysicalDeviceFeatures2() 
Wow, missed that one.

Fixes: 57e796a12a - ("radv: Implement VK_EXT_custom_border_color")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5128>
 2020-05-21 07:36:32 +00:00
Samuel Pitoiset 1ad9a8a884 aco: fix missing break in label_instruction() 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5129>
 2020-05-21 09:00:02 +02:00
Dave Airlie 22554e1fbc llvmpipe: compute shaders work better with all the threads. 
I got to benchmarking some vulkan compute benchmark and wondered
why my CPUs weren't being saturated, helps if you actually wake up
all the threads in the threadpool.

Fixes: 1b24e3ba75 (llvmpipe: add compute threadpool + mutex)

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5138>
 2020-05-21 14:10:41 +10:00
Nataraj Deshpande 02a1f95386 dri_util: Update internal_format to GL_RGB8 for MESA_FORMAT_R8G8B8X8_UNORM 
The commit helps to resolve GL_INVALID_OPERATION error returned
during CTS test when Android format RGBX8888 fallback to RGBA8888
and then set color with glTexSubImage2D(format=GL_RGB).

Fixes android.hardware.nativehardware.cts.AHardwareBufferNativeTests:
 #SingleLayer_ColorTest_GpuSampledImageCanBeSampled_R8G8B8X8_UNORM

Cc: <mesa-stable@lists.freedesktop.org>
Fixes: bf576772ab ("dri_util: add driImageFormatToSizedInternalGLFormat function")
Signed-off-by: Nataraj Deshpande <nataraj.deshpande@intel.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5034>
 2020-05-21 01:52:46 +00:00
Kristian H. Kristensen 13fc03f4c0 freedreno/a6xx: Avoid stalling for occlusion queries 
If we postpone computing the counter delta until after each tile (or
sysmem pass), we don't have to stall in the middle of the draw stream.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5064>
 2020-05-21 00:16:55 +00:00
Kristian H. Kristensen 1c21577246 freedreno/a6xx: Emit VFD setup as array writes 
We can use only one PKT4 for each of VFD_FETCH, VFD_DECODE and
VFD_DEST_CNTL and write all the elements if we split the loop into
three loops.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5064>
 2020-05-21 00:16:55 +00:00
Kristian H. Kristensen 5f494636fa freedreno/a6xx: Allocate ringbuffer based on VFD count 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5064>
 2020-05-21 00:16:55 +00:00
Kristian H. Kristensen 3275b8082a freedreno/a6xx: Map inputs to VFD entries up front 
Break this logic out of the loop in preperation for splitting the VFD
state emit loop up.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5064>
 2020-05-21 00:16:55 +00:00
Kristian H. Kristensen 5b7a73021c freedreno/a6xx: Create shader dependent streamout state at compile time 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5064>
 2020-05-21 00:16:55 +00:00
Eric Engestrom 9bac0dd99b compiler: delete leftover autotools test wrapper 
Signed-off-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5114>
 2020-05-20 22:19:30 +00:00
Eric Engestrom ba44990726 git_sha1_gen.py: fix whitespace 
Signed-off-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5112>
 2020-05-20 22:05:41 +00:00
Eric Engestrom c909370117 git_sha1_gen.py: fix code style 
Bare `except` are bad form as per PEP8.

Signed-off-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5112>
 2020-05-20 22:05:41 +00:00
Eric Engestrom 413c6f9905 git_sha1_gen.py: fix out-of-date comment 
This hasn't been true since 7088622e5f ("buildsys: move file
regeneration logic to the script itself") almost 3 years ago.

Signed-off-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5112>
 2020-05-20 22:05:41 +00:00
Eric Engestrom f68db81cbb anv: disable VK_EXT_calibrated_timestamps when the timestamp register is unreadable 
When running in a virtual context, the timestamp register is unreadable
on Gen12+.
While we could work around this, that would result in very inaccurate
results for an extension where the whole point is accuracy, so let's
just disable the extension.

Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/2797>
 2020-05-20 21:49:10 +00:00
Eric Engestrom a62ee262fd anv: replace magic | 1 with already #define'd name 
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/2797>
 2020-05-20 21:49:10 +00:00
Eric Engestrom e27f311c85 anv: pass the fd directly to anv_gem_reg_read() 
This allows its use without the need for an anv_device.

Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/2797>
 2020-05-20 21:49:10 +00:00
Eric Anholt 6bf40c28c9 ci: Make a530's GLES3/31 fractional runs much more complete. 
Now that we don't get scheduled to any 19mhz CPUs, the old GLES3 job went
from 12 minutes of deqp-runner runtime to 54s.  Increase how much of the
testsuite we cover in exchange, still keeping the runtime at 3-6 min
(compared to previous 10-17 min).  Since the tests we're running changed,
reset the xfails list.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5115>
 2020-05-20 21:05:32 +00:00
Eric Anholt 6033c10092 ci: Disable SMP on the a5xx boards. 
CPU0 comes up at some plausible freq, but the rest are at 19Mhz waiting
for cpufreq to come up, which has not been upstreamed.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5115>
 2020-05-20 21:05:32 +00:00