From ff52a724d41d429ed58e19c57d0ef82cba5f6a2e Mon Sep 17 00:00:00 2001 From: Rhys Perry Date: Mon, 21 Sep 2020 13:54:54 +0100 Subject: [PATCH] nir: add load_{scalar,vector}_arg_amd and load_smem_amd intrinsics MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit load_smem_gcn is similar to load_global/load_global_constant, but it's guaranteed to use SMEM and it's much easier to utilize the format's 32-bit offset source. Signed-off-by: Rhys Perry Reviewed-by: Samuel Pitoiset Reviewed-by: Timur Kristóf Part-of: --- src/compiler/nir/nir_divergence_analysis.c | 3 +++ src/compiler/nir/nir_intrinsics.py | 8 ++++++++ 2 files changed, 11 insertions(+) diff --git a/src/compiler/nir/nir_divergence_analysis.c b/src/compiler/nir/nir_divergence_analysis.c index 2ba6bcf7c5b..05a21a8d33a 100644 --- a/src/compiler/nir/nir_divergence_analysis.c +++ b/src/compiler/nir/nir_divergence_analysis.c @@ -159,6 +159,8 @@ visit_intrinsic(nir_shader *shader, nir_intrinsic_instr *instr) case nir_intrinsic_load_force_vrs_rates_amd: case nir_intrinsic_load_tess_level_inner_default: case nir_intrinsic_load_tess_level_outer_default: + case nir_intrinsic_load_scalar_arg_amd: + case nir_intrinsic_load_smem_amd: is_divergent = false; break; @@ -542,6 +544,7 @@ visit_intrinsic(nir_shader *shader, nir_intrinsic_instr *instr) case nir_intrinsic_gds_atomic_add_amd: case nir_intrinsic_load_rt_arg_scratch_offset_amd: case nir_intrinsic_load_intersection_opaque_amd: + case nir_intrinsic_load_vector_arg_amd: is_divergent = true; break; diff --git a/src/compiler/nir/nir_intrinsics.py b/src/compiler/nir/nir_intrinsics.py index 04192896b09..a4189f798b8 100644 --- a/src/compiler/nir/nir_intrinsics.py +++ b/src/compiler/nir/nir_intrinsics.py @@ -1330,6 +1330,14 @@ system_value("intersection_opaque_amd", 1, bit_sizes=[1]) # Load forced VRS rates. intrinsic("load_force_vrs_rates_amd", dest_comp=1, bit_sizes=[32], flags=[CAN_ELIMINATE, CAN_REORDER]) +intrinsic("load_scalar_arg_amd", dest_comp=0, bit_sizes=[32], indices=[BASE], flags=[CAN_ELIMINATE, CAN_REORDER]) +intrinsic("load_vector_arg_amd", dest_comp=0, bit_sizes=[32], indices=[BASE], flags=[CAN_ELIMINATE, CAN_REORDER]) + +# src[] = { 64-bit base address, 32-bit offset }. +intrinsic("load_smem_amd", src_comp=[1, 1], dest_comp=0, bit_sizes=[32], + indices=[ALIGN_MUL, ALIGN_OFFSET], + flags=[CAN_ELIMINATE, CAN_REORDER]) + # V3D-specific instrinc for tile buffer color reads. # # The hardware requires that we read the samples and components of a pixel