From fec2385301636fed6de740fe37dbefd06961c786 Mon Sep 17 00:00:00 2001 From: Samuel Pitoiset Date: Tue, 25 Jun 2024 11:37:14 +0200 Subject: [PATCH] radv: emit push constant for task shaders with DGC Signed-off-by: Samuel Pitoiset Part-of: --- .../vulkan/radv_device_generated_commands.c | 21 +++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/src/amd/vulkan/radv_device_generated_commands.c b/src/amd/vulkan/radv_device_generated_commands.c index 80dbdf8d7e0..148984132cb 100644 --- a/src/amd/vulkan/radv_device_generated_commands.c +++ b/src/amd/vulkan/radv_device_generated_commands.c @@ -2033,6 +2033,27 @@ build_dgc_prepare_shader(struct radv_device *dev) nir_def *stream_addr = load_param64(&b, stream_addr); stream_addr = nir_iadd(&b, stream_addr, nir_u2u64(&b, nir_imul(&b, sequence_id, stream_stride))); + nir_variable *upload_offset = + nir_variable_create(b.shader, nir_var_shader_temp, glsl_uint_type(), "upload_offset"); + nir_def *upload_offset_init = nir_iadd(&b, load_param32(&b, upload_main_offset), + nir_imul(&b, load_param32(&b, upload_stride), sequence_id)); + nir_store_var(&b, upload_offset, upload_offset_init, 0x1); + + nir_def *push_const_mask = load_param64(&b, push_constant_mask); + nir_push_if(&b, nir_ine_imm(&b, push_const_mask, 0)); + { + nir_def *push_constant_stages = dgc_get_push_constant_stages(&b, stream_addr); + + nir_push_if(&b, nir_test_mask(&b, push_constant_stages, VK_SHADER_STAGE_TASK_BIT_EXT)); + { + const struct dgc_pc_params params = dgc_get_pc_params(&b); + dgc_emit_push_constant_for_stage(&cmd_buf, stream_addr, push_const_mask, ¶ms, MESA_SHADER_TASK, + upload_offset); + } + nir_pop_if(&b, NULL); + } + nir_pop_if(&b, 0); + dgc_emit_draw_mesh_tasks_ace(&cmd_buf, stream_addr, load_param16(&b, draw_params_offset), sequence_id); /* Pad the cmdbuffer if we did not use the whole stride */