From fe128dca28c672f66e7b241420928816894484bd Mon Sep 17 00:00:00 2001
From: Jesse Natalie <jenatali@microsoft.com>
Date: Thu, 20 Apr 2023 07:41:02 -0700
Subject: [PATCH] spirv2dxil: Lower quad ops in non-fragment/compute stages

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22606>
---
 src/microsoft/spirv_to_dxil/dxil_spirv_nir.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/src/microsoft/spirv_to_dxil/dxil_spirv_nir.c b/src/microsoft/spirv_to_dxil/dxil_spirv_nir.c
index 43de9651282..b1026399cf7 100644
--- a/src/microsoft/spirv_to_dxil/dxil_spirv_nir.c
+++ b/src/microsoft/spirv_to_dxil/dxil_spirv_nir.c
@@ -946,6 +946,9 @@ dxil_spirv_nir_passes(nir_shader *nir,
       .lower_to_scalar = true,
       .lower_relative_shuffle = true,
    };
+   if (nir->info.stage != MESA_SHADER_FRAGMENT &&
+       nir->info.stage != MESA_SHADER_COMPUTE)
+      subgroup_options.lower_quad = true;
    NIR_PASS_V(nir, nir_lower_subgroups, &subgroup_options);
    NIR_PASS_V(nir, nir_lower_bit_size, lower_bit_size_callback, NULL);