intel/brw: Move and reduce scope of run_*() functions
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30169>
This commit is contained in:
@@ -2709,36 +2709,6 @@ fs_visitor::allocate_registers(bool allow_spilling)
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brw_fs_lower_scoreboard(*this);
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}
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bool
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fs_visitor::run_vs()
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{
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assert(stage == MESA_SHADER_VERTEX);
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payload_ = new vs_thread_payload(*this);
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nir_to_brw(this);
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if (failed)
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return false;
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emit_urb_writes();
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calculate_cfg();
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brw_fs_optimize(*this);
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assign_curb_setup();
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assign_vs_urb_setup();
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brw_fs_lower_3src_null_dest(*this);
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brw_fs_workaround_memory_fence_before_eot(*this);
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brw_fs_workaround_emit_dummy_mov_instruction(*this);
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allocate_registers(true /* allow_spilling */);
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return !failed;
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}
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void
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fs_visitor::set_tcs_invocation_id()
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{
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@@ -2811,370 +2781,6 @@ fs_visitor::emit_tcs_thread_end()
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inst->eot = true;
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}
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bool
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fs_visitor::run_tcs()
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{
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assert(stage == MESA_SHADER_TESS_CTRL);
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struct brw_vue_prog_data *vue_prog_data = brw_vue_prog_data(prog_data);
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const fs_builder bld = fs_builder(this).at_end();
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assert(vue_prog_data->dispatch_mode == INTEL_DISPATCH_MODE_TCS_SINGLE_PATCH ||
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vue_prog_data->dispatch_mode == INTEL_DISPATCH_MODE_TCS_MULTI_PATCH);
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payload_ = new tcs_thread_payload(*this);
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/* Initialize gl_InvocationID */
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set_tcs_invocation_id();
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const bool fix_dispatch_mask =
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vue_prog_data->dispatch_mode == INTEL_DISPATCH_MODE_TCS_SINGLE_PATCH &&
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(nir->info.tess.tcs_vertices_out % 8) != 0;
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/* Fix the disptach mask */
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if (fix_dispatch_mask) {
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bld.CMP(bld.null_reg_ud(), invocation_id,
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brw_imm_ud(nir->info.tess.tcs_vertices_out), BRW_CONDITIONAL_L);
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bld.IF(BRW_PREDICATE_NORMAL);
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}
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nir_to_brw(this);
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if (fix_dispatch_mask) {
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bld.emit(BRW_OPCODE_ENDIF);
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}
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emit_tcs_thread_end();
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if (failed)
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return false;
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calculate_cfg();
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brw_fs_optimize(*this);
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assign_curb_setup();
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assign_tcs_urb_setup();
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brw_fs_lower_3src_null_dest(*this);
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brw_fs_workaround_memory_fence_before_eot(*this);
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brw_fs_workaround_emit_dummy_mov_instruction(*this);
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allocate_registers(true /* allow_spilling */);
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return !failed;
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}
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bool
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fs_visitor::run_tes()
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{
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assert(stage == MESA_SHADER_TESS_EVAL);
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payload_ = new tes_thread_payload(*this);
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nir_to_brw(this);
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if (failed)
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return false;
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emit_urb_writes();
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calculate_cfg();
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brw_fs_optimize(*this);
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assign_curb_setup();
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assign_tes_urb_setup();
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brw_fs_lower_3src_null_dest(*this);
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brw_fs_workaround_memory_fence_before_eot(*this);
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brw_fs_workaround_emit_dummy_mov_instruction(*this);
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allocate_registers(true /* allow_spilling */);
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return !failed;
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}
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bool
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fs_visitor::run_gs()
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{
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assert(stage == MESA_SHADER_GEOMETRY);
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payload_ = new gs_thread_payload(*this);
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const fs_builder bld = fs_builder(this).at_end();
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this->final_gs_vertex_count = bld.vgrf(BRW_TYPE_UD);
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if (gs_compile->control_data_header_size_bits > 0) {
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/* Create a VGRF to store accumulated control data bits. */
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this->control_data_bits = bld.vgrf(BRW_TYPE_UD);
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/* If we're outputting more than 32 control data bits, then EmitVertex()
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* will set control_data_bits to 0 after emitting the first vertex.
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* Otherwise, we need to initialize it to 0 here.
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*/
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if (gs_compile->control_data_header_size_bits <= 32) {
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const fs_builder abld = bld.annotate("initialize control data bits");
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abld.MOV(this->control_data_bits, brw_imm_ud(0u));
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}
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}
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nir_to_brw(this);
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emit_gs_thread_end();
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if (failed)
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return false;
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calculate_cfg();
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brw_fs_optimize(*this);
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assign_curb_setup();
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assign_gs_urb_setup();
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brw_fs_lower_3src_null_dest(*this);
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brw_fs_workaround_memory_fence_before_eot(*this);
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brw_fs_workaround_emit_dummy_mov_instruction(*this);
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allocate_registers(true /* allow_spilling */);
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return !failed;
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}
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/* From the SKL PRM, Volume 16, Workarounds:
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*
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* 0877 3D Pixel Shader Hang possible when pixel shader dispatched with
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* only header phases (R0-R2)
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*
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* WA: Enable a non-header phase (e.g. push constant) when dispatch would
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* have been header only.
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*
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* Instead of enabling push constants one can alternatively enable one of the
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* inputs. Here one simply chooses "layer" which shouldn't impose much
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* overhead.
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*/
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static void
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gfx9_ps_header_only_workaround(struct brw_wm_prog_data *wm_prog_data)
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{
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if (wm_prog_data->num_varying_inputs)
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return;
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if (wm_prog_data->base.curb_read_length)
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return;
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wm_prog_data->urb_setup[VARYING_SLOT_LAYER] = 0;
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wm_prog_data->num_varying_inputs = 1;
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brw_compute_urb_setup_index(wm_prog_data);
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}
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bool
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fs_visitor::run_fs(bool allow_spilling, bool do_rep_send)
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{
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struct brw_wm_prog_data *wm_prog_data = brw_wm_prog_data(this->prog_data);
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brw_wm_prog_key *wm_key = (brw_wm_prog_key *) this->key;
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const fs_builder bld = fs_builder(this).at_end();
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assert(stage == MESA_SHADER_FRAGMENT);
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payload_ = new fs_thread_payload(*this, source_depth_to_render_target);
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if (nir->info.ray_queries > 0)
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limit_dispatch_width(16, "SIMD32 not supported with ray queries.\n");
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if (do_rep_send) {
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assert(dispatch_width == 16);
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emit_repclear_shader();
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} else {
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if (nir->info.inputs_read > 0 ||
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BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_FRAG_COORD) ||
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(nir->info.outputs_read > 0 && !wm_key->coherent_fb_fetch)) {
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emit_interpolation_setup();
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}
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/* We handle discards by keeping track of the still-live pixels in f0.1.
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* Initialize it with the dispatched pixels.
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*/
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if (devinfo->ver >= 20 || wm_prog_data->uses_kill) {
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const unsigned lower_width = MIN2(dispatch_width, 16);
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for (unsigned i = 0; i < dispatch_width / lower_width; i++) {
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/* According to the "PS Thread Payload for Normal
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* Dispatch" pages on the BSpec, the dispatch mask is
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* stored in R0.15/R1.15 on gfx20+ and in R1.7/R2.7 on
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* gfx6+.
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*/
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const brw_reg dispatch_mask =
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devinfo->ver >= 20 ? xe2_vec1_grf(i, 15) :
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brw_vec1_grf(i + 1, 7);
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bld.exec_all().group(1, 0)
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.MOV(brw_sample_mask_reg(bld.group(lower_width, i)),
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retype(dispatch_mask, BRW_TYPE_UW));
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}
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}
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if (nir->info.writes_memory)
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wm_prog_data->has_side_effects = true;
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nir_to_brw(this);
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if (failed)
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return false;
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emit_fb_writes();
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calculate_cfg();
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brw_fs_optimize(*this);
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assign_curb_setup();
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if (devinfo->ver == 9)
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gfx9_ps_header_only_workaround(wm_prog_data);
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assign_urb_setup();
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brw_fs_lower_3src_null_dest(*this);
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brw_fs_workaround_memory_fence_before_eot(*this);
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brw_fs_workaround_emit_dummy_mov_instruction(*this);
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allocate_registers(allow_spilling);
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}
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return !failed;
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}
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bool
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fs_visitor::run_cs(bool allow_spilling)
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{
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assert(gl_shader_stage_is_compute(stage));
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const fs_builder bld = fs_builder(this).at_end();
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payload_ = new cs_thread_payload(*this);
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if (devinfo->platform == INTEL_PLATFORM_HSW && prog_data->total_shared > 0) {
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/* Move SLM index from g0.0[27:24] to sr0.1[11:8] */
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const fs_builder abld = bld.exec_all().group(1, 0);
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abld.MOV(retype(brw_sr0_reg(1), BRW_TYPE_UW),
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suboffset(retype(brw_vec1_grf(0, 0), BRW_TYPE_UW), 1));
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}
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nir_to_brw(this);
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if (failed)
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return false;
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emit_cs_terminate();
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calculate_cfg();
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brw_fs_optimize(*this);
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assign_curb_setup();
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brw_fs_lower_3src_null_dest(*this);
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brw_fs_workaround_memory_fence_before_eot(*this);
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brw_fs_workaround_emit_dummy_mov_instruction(*this);
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allocate_registers(allow_spilling);
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return !failed;
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}
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bool
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fs_visitor::run_bs(bool allow_spilling)
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{
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assert(stage >= MESA_SHADER_RAYGEN && stage <= MESA_SHADER_CALLABLE);
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payload_ = new bs_thread_payload(*this);
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nir_to_brw(this);
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if (failed)
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return false;
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/* TODO(RT): Perhaps rename this? */
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emit_cs_terminate();
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calculate_cfg();
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brw_fs_optimize(*this);
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assign_curb_setup();
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brw_fs_lower_3src_null_dest(*this);
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brw_fs_workaround_memory_fence_before_eot(*this);
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brw_fs_workaround_emit_dummy_mov_instruction(*this);
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allocate_registers(allow_spilling);
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return !failed;
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}
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bool
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fs_visitor::run_task(bool allow_spilling)
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{
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assert(stage == MESA_SHADER_TASK);
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payload_ = new task_mesh_thread_payload(*this);
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nir_to_brw(this);
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if (failed)
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return false;
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emit_urb_fence();
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emit_cs_terminate();
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calculate_cfg();
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brw_fs_optimize(*this);
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assign_curb_setup();
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brw_fs_lower_3src_null_dest(*this);
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brw_fs_workaround_memory_fence_before_eot(*this);
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brw_fs_workaround_emit_dummy_mov_instruction(*this);
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allocate_registers(allow_spilling);
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return !failed;
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}
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bool
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fs_visitor::run_mesh(bool allow_spilling)
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{
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assert(stage == MESA_SHADER_MESH);
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payload_ = new task_mesh_thread_payload(*this);
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nir_to_brw(this);
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if (failed)
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return false;
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emit_urb_fence();
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emit_cs_terminate();
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calculate_cfg();
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brw_fs_optimize(*this);
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assign_curb_setup();
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brw_fs_lower_3src_null_dest(*this);
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brw_fs_workaround_memory_fence_before_eot(*this);
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brw_fs_workaround_emit_dummy_mov_instruction(*this);
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allocate_registers(allow_spilling);
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return !failed;
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}
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/**
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* Move load_interpolated_input with simple (payload-based) barycentric modes
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* to the top of the program so we don't emit multiple PLNs for the same input.
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