From fd4a44430c94690a46f6e962582382c41190c2a1 Mon Sep 17 00:00:00 2001 From: Paulo Zanoni Date: Mon, 5 Aug 2024 16:09:01 -0700 Subject: [PATCH] anv: remove duplicate pipe_control workaround MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Commit a603cc06334f ("anv: move some pc was to batch_emit_pipe_control_write") moved some WAs from emit_apply_pipe_flushes() to batch_emit_pipe_control_write(), but it turns out one of them was already there since cf7e1f3817d4 ("anv, iris: add missing CS_STALL bit for GPGPU texture invalidation"). Reviewed-by: Tapani Pälli Reviewed-by: Lionel Landwerlin Signed-off-by: Paulo Zanoni Part-of: --- src/intel/vulkan/genX_cmd_buffer.c | 14 -------------- 1 file changed, 14 deletions(-) diff --git a/src/intel/vulkan/genX_cmd_buffer.c b/src/intel/vulkan/genX_cmd_buffer.c index df1a7f3face..5860c98c35d 100644 --- a/src/intel/vulkan/genX_cmd_buffer.c +++ b/src/intel/vulkan/genX_cmd_buffer.c @@ -2515,20 +2515,6 @@ genX(batch_emit_pipe_control_write)(struct anv_batch *batch, if (GFX_VER == 9 && (bits & ANV_PIPE_VF_CACHE_INVALIDATE_BIT)) anv_batch_emit(batch, GENX(PIPE_CONTROL), pipe); -#if GFX_VER >= 9 && GFX_VER <= 11 - /* From the SKL PRM, Vol. 2a, "PIPE_CONTROL", - * - * "Workaround : “CS Stall” bit in PIPE_CONTROL command must be - * always set for GPGPU workloads when “Texture Cache - * Invalidation Enable” bit is set". - * - * Workaround stopped appearing in TGL PRMs. - */ - if (current_pipeline == GPGPU && - (bits & ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT)) - bits |= ANV_PIPE_CS_STALL_BIT; -#endif - anv_batch_emit(batch, GENX(PIPE_CONTROL), pipe) { #if GFX_VERx10 >= 125 pipe.UntypedDataPortCacheFlushEnable =