brw: handle wa_18019110168 with independent shader compilation

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35103>

src/compiler/nir/nir_divergence_analysis.c

@@ -361,6 +361,7 @@ visit_intrinsic(nir_intrinsic_instr *instr, struct divergence_state *state)
    case nir_intrinsic_load_max_polygon_intel:
    case nir_intrinsic_load_ray_base_mem_addr_intel:
    case nir_intrinsic_load_ray_hw_stack_size_intel:
+   case nir_intrinsic_load_per_primitive_remap_intel:
       is_divergent = false;
       break;
 

src/compiler/nir/nir_intrinsics.py

@@ -2336,6 +2336,10 @@ intrinsic("read_attribute_payload_intel", dest_comp=1, bit_sizes=[32],
           src_comp=[1],
           flags=[CAN_ELIMINATE, CAN_REORDER])
 
+# Populate the per-primitive payload at an offset
+# src[] = { value, offset }
+intrinsic("store_per_primitive_payload_intel", src_comp=[-1], indices=[BASE, COMPONENT])
+
 # Number of data items being operated on for a SIMD program.
 system_value("simd_width_intel", 1)
 
@@ -2417,6 +2421,9 @@ intrinsic("load_inline_data_intel", [], dest_comp=0,
 # Dynamic fragment shader parameters.
 system_value("fs_msaa_intel", 1)
 
+# Per primitive remapping table offset.
+system_value("per_primitive_remap_intel", 1)
+
 # Intrinsics for Intel bindless thread dispatch
 # BASE=brw_topoloy_id
 system_value("topology_id_intel", 1, indices=[BASE])