From fcaa9f509622e7367541748eb6457e6869bf6dcf Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Marek=20Ol=C5=A1=C3=A1k?= Date: Fri, 13 May 2022 22:34:17 -0400 Subject: [PATCH] radeonsi/gfx11: fix alpha-to-coverage with stencil or samplemask export We can't use UINT16_ABGR for the alpha channel. Always use 32_ABGR. Reviewed-by: Mihai Preda Reviewed-by: Pierre-Eric Pelloux-Prayer Part-of: --- src/amd/common/ac_shader_util.c | 10 +++++++--- src/amd/common/ac_shader_util.h | 3 ++- src/amd/llvm/ac_llvm_build.c | 20 +++++-------------- src/amd/llvm/ac_llvm_build.h | 2 +- src/amd/vulkan/radv_pipeline.c | 2 +- .../drivers/radeonsi/si_state_shaders.cpp | 3 ++- 6 files changed, 18 insertions(+), 22 deletions(-) diff --git a/src/amd/common/ac_shader_util.c b/src/amd/common/ac_shader_util.c index 33002f78d95..c468715e658 100644 --- a/src/amd/common/ac_shader_util.c +++ b/src/amd/common/ac_shader_util.c @@ -31,11 +31,15 @@ #include #include -unsigned ac_get_spi_shader_z_format(bool writes_z, bool writes_stencil, bool writes_samplemask) +unsigned ac_get_spi_shader_z_format(bool writes_z, bool writes_stencil, bool writes_samplemask, + bool writes_mrt0_alpha) { - if (writes_z) { + /* If writes_mrt0_alpha is true, one other flag must be true too. */ + assert(!writes_mrt0_alpha || writes_z || writes_stencil || writes_samplemask); + + if (writes_z || writes_mrt0_alpha) { /* Z needs 32 bits. */ - if (writes_samplemask) + if (writes_samplemask || writes_mrt0_alpha) return V_028710_SPI_SHADER_32_ABGR; else if (writes_stencil) return V_028710_SPI_SHADER_32_GR; diff --git a/src/amd/common/ac_shader_util.h b/src/amd/common/ac_shader_util.h index 37252fe1f8e..e0c90765ef0 100644 --- a/src/amd/common/ac_shader_util.h +++ b/src/amd/common/ac_shader_util.h @@ -90,7 +90,8 @@ enum ac_descriptor_type AC_DESC_PLANE_2, }; -unsigned ac_get_spi_shader_z_format(bool writes_z, bool writes_stencil, bool writes_samplemask); +unsigned ac_get_spi_shader_z_format(bool writes_z, bool writes_stencil, bool writes_samplemask, + bool writes_mrt0_alpha); unsigned ac_get_cb_shader_mask(unsigned spi_shader_col_format); diff --git a/src/amd/llvm/ac_llvm_build.c b/src/amd/llvm/ac_llvm_build.c index e29fb751c1a..9401ed27a52 100644 --- a/src/amd/llvm/ac_llvm_build.c +++ b/src/amd/llvm/ac_llvm_build.c @@ -4290,11 +4290,12 @@ LLVMValueRef ac_build_call(struct ac_llvm_context *ctx, LLVMValueRef func, LLVMV } void ac_export_mrt_z(struct ac_llvm_context *ctx, LLVMValueRef depth, LLVMValueRef stencil, - LLVMValueRef samplemask, LLVMValueRef mrtz_alpha, bool is_last, + LLVMValueRef samplemask, LLVMValueRef mrt0_alpha, bool is_last, struct ac_export_args *args) { unsigned mask = 0; - unsigned format = ac_get_spi_shader_z_format(depth != NULL, stencil != NULL, samplemask != NULL); + unsigned format = ac_get_spi_shader_z_format(depth != NULL, stencil != NULL, samplemask != NULL, + mrt0_alpha != NULL); assert(depth || stencil || samplemask); @@ -4330,17 +4331,6 @@ void ac_export_mrt_z(struct ac_llvm_context *ctx, LLVMValueRef depth, LLVMValueR args->out[1] = samplemask; mask |= ctx->gfx_level >= GFX11 ? 0x2 : 0xc; } - if (mrtz_alpha) { - /* MRT0 alpha should be in Y[31:16] if alpha-to-coverage is enabled and MRTZ is present. */ - assert(ctx->gfx_level >= GFX11); - mrtz_alpha = LLVMBuildFPTrunc(ctx->builder, mrtz_alpha, ctx->f16, ""); - mrtz_alpha = ac_to_integer(ctx, mrtz_alpha); - mrtz_alpha = LLVMBuildZExt(ctx->builder, mrtz_alpha, ctx->i32, ""); - mrtz_alpha = LLVMBuildShl(ctx->builder, mrtz_alpha, LLVMConstInt(ctx->i32, 16, 0), ""); - args->out[1] = LLVMBuildOr(ctx->builder, ac_to_integer(ctx, args->out[1]), mrtz_alpha, ""); - args->out[1] = ac_to_float(ctx, args->out[1]); - mask |= 0x2; - } } else { if (depth) { args->out[0] = depth; @@ -4354,8 +4344,8 @@ void ac_export_mrt_z(struct ac_llvm_context *ctx, LLVMValueRef depth, LLVMValueR args->out[2] = samplemask; mask |= 0x4; } - if (mrtz_alpha) { - args->out[3] = mrtz_alpha; + if (mrt0_alpha) { + args->out[3] = mrt0_alpha; mask |= 0x8; } } diff --git a/src/amd/llvm/ac_llvm_build.h b/src/amd/llvm/ac_llvm_build.h index c268d7673cb..0b871e78fc5 100644 --- a/src/amd/llvm/ac_llvm_build.h +++ b/src/amd/llvm/ac_llvm_build.h @@ -556,7 +556,7 @@ LLVMValueRef ac_build_atomic_cmp_xchg(struct ac_llvm_context *ctx, LLVMValueRef LLVMValueRef cmp, LLVMValueRef val, const char *sync_scope); void ac_export_mrt_z(struct ac_llvm_context *ctx, LLVMValueRef depth, LLVMValueRef stencil, - LLVMValueRef samplemask, LLVMValueRef mrtz_alpha, bool is_last, + LLVMValueRef samplemask, LLVMValueRef mrt0_alpha, bool is_last, struct ac_export_args *args); void ac_build_sendmsg_gs_alloc_req(struct ac_llvm_context *ctx, LLVMValueRef wave_id, diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c index 16bee2dcc6f..569740b9cd0 100644 --- a/src/amd/vulkan/radv_pipeline.c +++ b/src/amd/vulkan/radv_pipeline.c @@ -6208,7 +6208,7 @@ radv_pipeline_generate_fragment_shader(struct radeon_cmdbuf *ctx_cs, struct rade radeon_set_context_reg( ctx_cs, R_028710_SPI_SHADER_Z_FORMAT, ac_get_spi_shader_z_format(ps->info.ps.writes_z, ps->info.ps.writes_stencil, - ps->info.ps.writes_sample_mask)); + ps->info.ps.writes_sample_mask, false)); } static void diff --git a/src/gallium/drivers/radeonsi/si_state_shaders.cpp b/src/gallium/drivers/radeonsi/si_state_shaders.cpp index 23970d9a212..8d70cfcba90 100644 --- a/src/gallium/drivers/radeonsi/si_state_shaders.cpp +++ b/src/gallium/drivers/radeonsi/si_state_shaders.cpp @@ -1943,7 +1943,8 @@ static void si_shader_ps(struct si_screen *sscreen, struct si_shader *shader) shader->ctx_reg.ps.spi_baryc_cntl = spi_baryc_cntl; shader->ctx_reg.ps.spi_ps_in_control = spi_ps_in_control; shader->ctx_reg.ps.spi_shader_z_format = - ac_get_spi_shader_z_format(info->writes_z, info->writes_stencil, info->writes_samplemask); + ac_get_spi_shader_z_format(info->writes_z, info->writes_stencil, info->writes_samplemask, + shader->key.ps.part.epilog.alpha_to_coverage_via_mrtz); shader->ctx_reg.ps.spi_shader_col_format = spi_shader_col_format; shader->ctx_reg.ps.cb_shader_mask = cb_shader_mask;