diff --git a/src/amd/compiler/aco_instruction_selection.cpp b/src/amd/compiler/aco_instruction_selection.cpp
index e70fb60e424..57b0e481607 100644
--- a/src/amd/compiler/aco_instruction_selection.cpp
+++ b/src/amd/compiler/aco_instruction_selection.cpp
@@ -11458,6 +11458,14 @@ get_tess_ring_descriptor(isel_context* ctx, const struct aco_tcs_epilog_info* ei
 {
    Builder bld(ctx->program, ctx->block);
 
+   if (!ctx->options->is_opengl) {
+      Temp ring_offsets = get_arg(ctx, ctx->args->ring_offsets);
+      uint32_t tess_ring_offset =
+         is_tcs_factor_ring ? 5 /* RING_HS_TESS_FACTOR */ : 6 /* RING_HS_TESS_OFFCHIP */;
+      return bld.smem(aco_opcode::s_load_dwordx4, bld.def(s4), ring_offsets,
+                      Operand::c32(tess_ring_offset * 16u));
+   }
+
    Temp addr = get_arg(ctx, einfo->tcs_out_lds_layout);
    /* TCS only receives high 13 bits of the address. */
    addr = bld.sop2(aco_opcode::s_and_b32, bld.def(s1), bld.def(s1, scc), addr,
@@ -12312,13 +12320,22 @@ select_tcs_epilog(Program* program, void* pinfo, ac_shader_config* config,
 
    if (einfo->tes_reads_tessfactors) {
       Temp layout = get_arg(&ctx, einfo->tcs_offchip_layout);
-      Temp num_patches =
-         bld.sop2(aco_opcode::s_and_b32, bld.def(s1), bld.def(s1, scc), layout, Operand::c32(0x3f));
-      num_patches = bld.sop2(aco_opcode::s_add_u32, bld.def(s1), bld.def(s1, scc), num_patches,
-                             Operand::c32(1));
+      Temp num_patches, patch_base;
 
-      Temp patch_base =
-         bld.sop2(aco_opcode::s_lshr_b32, bld.def(s1), bld.def(s1, scc), layout, Operand::c32(16));
+      if (ctx.options->is_opengl) {
+         num_patches = bld.sop2(aco_opcode::s_and_b32, bld.def(s1), bld.def(s1, scc), layout,
+                                Operand::c32(0x3f));
+         num_patches = bld.sop2(aco_opcode::s_add_u32, bld.def(s1), bld.def(s1, scc), num_patches,
+                                Operand::c32(1));
+
+         patch_base = bld.sop2(aco_opcode::s_lshr_b32, bld.def(s1), bld.def(s1, scc), layout,
+                               Operand::c32(16));
+      } else {
+         num_patches = bld.sop2(aco_opcode::s_bfe_u32, bld.def(s1), bld.def(s1, scc), layout,
+                                Operand::c32(0x60006));
+
+         patch_base = get_arg(&ctx, einfo->patch_base);
+      }
 
       Temp tess_ring_desc = get_tess_ring_descriptor(&ctx, einfo, false);
       Temp tess_ring_base = get_arg(&ctx, args->tess_offchip_offset);
diff --git a/src/amd/compiler/aco_shader_info.h b/src/amd/compiler/aco_shader_info.h
index 952f980a0af..d9d7c17c8f3 100644
--- a/src/amd/compiler/aco_shader_info.h
+++ b/src/amd/compiler/aco_shader_info.h
@@ -87,6 +87,7 @@ struct aco_tcs_epilog_info {
    struct ac_arg invocation_id;
    struct ac_arg rel_patch_id;
    struct ac_arg tcs_out_current_patch_data_offset;
+   struct ac_arg patch_base;
    struct ac_arg tess_lvl_in[2];
    struct ac_arg tess_lvl_out[4];
    struct ac_arg tcs_out_lds_layout;