From faf10bd49d385d02dcad524c02151674b7c6d7ce Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Marek=20Ol=C5=A1=C3=A1k?= Date: Mon, 12 Apr 2021 01:54:07 -0400 Subject: [PATCH] ac/surface: use named "color and "zs" structures in unions Reviewed-by: Pierre-Eric Pelloux-Prayer Part-of: --- src/amd/common/ac_surface.c | 246 +++++++++--------- src/amd/common/ac_surface.h | 8 +- src/amd/common/ac_surface_modifier_test.c | 16 +- src/amd/vulkan/radv_cmd_buffer.c | 2 +- src/amd/vulkan/radv_device.c | 40 +-- src/amd/vulkan/radv_image.c | 40 +-- src/amd/vulkan/radv_meta_clear.c | 4 +- src/amd/vulkan/radv_meta_dcc_retile.c | 6 +- src/gallium/drivers/r600/evergreen_state.c | 4 +- src/gallium/drivers/r600/r600_texture.c | 12 +- src/gallium/drivers/radeonsi/si_blit.c | 2 +- src/gallium/drivers/radeonsi/si_clear.c | 6 +- .../drivers/radeonsi/si_compute_blit.c | 14 +- src/gallium/drivers/radeonsi/si_descriptors.c | 14 +- src/gallium/drivers/radeonsi/si_pipe.h | 2 +- src/gallium/drivers/radeonsi/si_state.c | 52 ++-- src/gallium/drivers/radeonsi/si_texture.c | 26 +- .../winsys/radeon/drm/radeon_drm_surface.c | 26 +- 18 files changed, 260 insertions(+), 260 deletions(-) diff --git a/src/amd/common/ac_surface.c b/src/amd/common/ac_surface.c index 459d40cfe56..55519b692d8 100644 --- a/src/amd/common/ac_surface.c +++ b/src/amd/common/ac_surface.c @@ -358,9 +358,9 @@ ac_modifier_fill_dcc_params(uint64_t modifier, struct radeon_surf *surf, surf_info->flags.metaPipeUnaligned = !AMD_FMT_MOD_GET(DCC_PIPE_ALIGN, modifier); } - surf->u.gfx9.dcc.independent_64B_blocks = AMD_FMT_MOD_GET(DCC_INDEPENDENT_64B, modifier); - surf->u.gfx9.dcc.independent_128B_blocks = AMD_FMT_MOD_GET(DCC_INDEPENDENT_128B, modifier); - surf->u.gfx9.dcc.max_compressed_block_size = AMD_FMT_MOD_GET(DCC_MAX_COMPRESSED_BLOCK, modifier); + surf->u.gfx9.color.dcc.independent_64B_blocks = AMD_FMT_MOD_GET(DCC_INDEPENDENT_64B, modifier); + surf->u.gfx9.color.dcc.independent_128B_blocks = AMD_FMT_MOD_GET(DCC_INDEPENDENT_128B, modifier); + surf->u.gfx9.color.dcc.max_compressed_block_size = AMD_FMT_MOD_GET(DCC_MAX_COMPRESSED_BLOCK, modifier); } bool ac_is_modifier_supported(const struct radeon_info *info, @@ -781,7 +781,7 @@ static int gfx6_compute_level(ADDR_HANDLE addrlib, const struct ac_surf_config * /* Set the base level pitch. This is needed for calculation * of non-zero levels. */ if (is_stencil) - AddrSurfInfoIn->basePitch = surf->u.legacy.stencil_level[0].nblk_x; + AddrSurfInfoIn->basePitch = surf->u.legacy.zs.stencil_level[0].nblk_x; else AddrSurfInfoIn->basePitch = surf->u.legacy.level[0].nblk_x; @@ -795,8 +795,8 @@ static int gfx6_compute_level(ADDR_HANDLE addrlib, const struct ac_surf_config * return ret; } - surf_level = is_stencil ? &surf->u.legacy.stencil_level[level] : &surf->u.legacy.level[level]; - dcc_level = &surf->u.legacy.dcc_level[level]; + surf_level = is_stencil ? &surf->u.legacy.zs.stencil_level[level] : &surf->u.legacy.level[level]; + dcc_level = &surf->u.legacy.color.dcc_level[level]; surf_level->offset_256B = align64(surf->surf_size, AddrSurfInfoOut->baseAlign) / 256; surf_level->slice_size_dw = AddrSurfInfoOut->sliceSize / 4; surf_level->nblk_x = AddrSurfInfoOut->pitch; @@ -819,7 +819,7 @@ static int gfx6_compute_level(ADDR_HANDLE addrlib, const struct ac_surf_config * } if (is_stencil) - surf->u.legacy.stencil_tiling_index[level] = AddrSurfInfoOut->tileIndex; + surf->u.legacy.zs.stencil_tiling_index[level] = AddrSurfInfoOut->tileIndex; else surf->u.legacy.tiling_index[level] = AddrSurfInfoOut->tileIndex; @@ -1096,9 +1096,9 @@ static void ac_compute_cmask(const struct radeon_info *info, const struct ac_sur /* Each element of CMASK is a nibble. */ unsigned slice_bytes = slice_elements / 2; - surf->u.legacy.cmask_slice_tile_max = (width * height) / (128 * 128); - if (surf->u.legacy.cmask_slice_tile_max) - surf->u.legacy.cmask_slice_tile_max -= 1; + surf->u.legacy.color.cmask_slice_tile_max = (width * height) / (128 * 128); + if (surf->u.legacy.color.cmask_slice_tile_max) + surf->u.legacy.color.cmask_slice_tile_max -= 1; unsigned num_layers; if (config->is_3d) @@ -1381,10 +1381,10 @@ static int gfx6_compute_surface(ADDR_HANDLE addrlib, const struct radeon_info *i /* DB uses the depth pitch for both stencil and depth. */ if (!only_stencil) { - if (surf->u.legacy.stencil_level[level].nblk_x != surf->u.legacy.level[level].nblk_x) + if (surf->u.legacy.zs.stencil_level[level].nblk_x != surf->u.legacy.level[level].nblk_x) surf->u.legacy.stencil_adjusted = true; } else { - surf->u.legacy.level[level].nblk_x = surf->u.legacy.stencil_level[level].nblk_x; + surf->u.legacy.level[level].nblk_x = surf->u.legacy.zs.stencil_level[level].nblk_x; } if (level == 0) { @@ -1430,13 +1430,13 @@ static int gfx6_compute_surface(ADDR_HANDLE addrlib, const struct radeon_info *i surf->fmask_slice_size = fout.sliceSize; surf->fmask_tile_swizzle = 0; - surf->u.legacy.fmask.slice_tile_max = (fout.pitch * fout.height) / 64; - if (surf->u.legacy.fmask.slice_tile_max) - surf->u.legacy.fmask.slice_tile_max -= 1; + surf->u.legacy.color.fmask.slice_tile_max = (fout.pitch * fout.height) / 64; + if (surf->u.legacy.color.fmask.slice_tile_max) + surf->u.legacy.color.fmask.slice_tile_max -= 1; - surf->u.legacy.fmask.tiling_index = fout.tileIndex; - surf->u.legacy.fmask.bankh = fout.pTileInfo->bankHeight; - surf->u.legacy.fmask.pitch_in_pixels = fout.pitch; + surf->u.legacy.color.fmask.tiling_index = fout.tileIndex; + surf->u.legacy.color.fmask.bankh = fout.pTileInfo->bankHeight; + surf->u.legacy.color.fmask.pitch_in_pixels = fout.pitch; /* Compute tile swizzle for FMASK. */ if (config->info.fmask_surf_index && !(surf->flags & RADEON_SURF_SHAREABLE)) { @@ -1606,33 +1606,33 @@ ASSERTED static bool is_dcc_supported_by_L2(const struct radeon_info *info, { if (info->chip_class <= GFX9) { /* Only independent 64B blocks are supported. */ - return surf->u.gfx9.dcc.independent_64B_blocks && !surf->u.gfx9.dcc.independent_128B_blocks && - surf->u.gfx9.dcc.max_compressed_block_size == V_028C78_MAX_BLOCK_SIZE_64B; + return surf->u.gfx9.color.dcc.independent_64B_blocks && !surf->u.gfx9.color.dcc.independent_128B_blocks && + surf->u.gfx9.color.dcc.max_compressed_block_size == V_028C78_MAX_BLOCK_SIZE_64B; } if (info->family == CHIP_NAVI10) { /* Only independent 128B blocks are supported. */ - return !surf->u.gfx9.dcc.independent_64B_blocks && surf->u.gfx9.dcc.independent_128B_blocks && - surf->u.gfx9.dcc.max_compressed_block_size <= V_028C78_MAX_BLOCK_SIZE_128B; + return !surf->u.gfx9.color.dcc.independent_64B_blocks && surf->u.gfx9.color.dcc.independent_128B_blocks && + surf->u.gfx9.color.dcc.max_compressed_block_size <= V_028C78_MAX_BLOCK_SIZE_128B; } if (info->family == CHIP_NAVI12 || info->family == CHIP_NAVI14) { /* Either 64B or 128B can be used, but not both. * If 64B is used, DCC image stores are unsupported. */ - return surf->u.gfx9.dcc.independent_64B_blocks != surf->u.gfx9.dcc.independent_128B_blocks && - (!surf->u.gfx9.dcc.independent_64B_blocks || - surf->u.gfx9.dcc.max_compressed_block_size == V_028C78_MAX_BLOCK_SIZE_64B) && - (!surf->u.gfx9.dcc.independent_128B_blocks || - surf->u.gfx9.dcc.max_compressed_block_size <= V_028C78_MAX_BLOCK_SIZE_128B); + return surf->u.gfx9.color.dcc.independent_64B_blocks != surf->u.gfx9.color.dcc.independent_128B_blocks && + (!surf->u.gfx9.color.dcc.independent_64B_blocks || + surf->u.gfx9.color.dcc.max_compressed_block_size == V_028C78_MAX_BLOCK_SIZE_64B) && + (!surf->u.gfx9.color.dcc.independent_128B_blocks || + surf->u.gfx9.color.dcc.max_compressed_block_size <= V_028C78_MAX_BLOCK_SIZE_128B); } /* 128B is recommended, but 64B can be set too if needed for 4K by DCN. * Since there is no reason to ever disable 128B, require it. * DCC image stores are always supported. */ - return surf->u.gfx9.dcc.independent_128B_blocks && - surf->u.gfx9.dcc.max_compressed_block_size <= V_028C78_MAX_BLOCK_SIZE_128B; + return surf->u.gfx9.color.dcc.independent_128B_blocks && + surf->u.gfx9.color.dcc.max_compressed_block_size <= V_028C78_MAX_BLOCK_SIZE_128B; } static bool is_dcc_supported_by_DCN(const struct radeon_info *info, @@ -1657,19 +1657,19 @@ static bool is_dcc_supported_by_DCN(const struct radeon_info *info, * INDEPENDENT_64B_BLOCKS = 1 and MAX_COMPRESSED_BLOCK_SIZE = 64B, * which always works. */ - assert(surf->u.gfx9.dcc.independent_64B_blocks && - surf->u.gfx9.dcc.max_compressed_block_size == V_028C78_MAX_BLOCK_SIZE_64B); + assert(surf->u.gfx9.color.dcc.independent_64B_blocks && + surf->u.gfx9.color.dcc.max_compressed_block_size == V_028C78_MAX_BLOCK_SIZE_64B); return true; case GFX10: case GFX10_3: /* DCN requires INDEPENDENT_128B_BLOCKS = 0 only on Navi1x. */ - if (info->chip_class == GFX10 && surf->u.gfx9.dcc.independent_128B_blocks) + if (info->chip_class == GFX10 && surf->u.gfx9.color.dcc.independent_128B_blocks) return false; /* For 4K, DCN requires INDEPENDENT_64B_BLOCKS = 1. */ return ((config->info.width <= 2560 && config->info.height <= 2560) || - (surf->u.gfx9.dcc.independent_64B_blocks && - surf->u.gfx9.dcc.max_compressed_block_size == V_028C78_MAX_BLOCK_SIZE_64B)); + (surf->u.gfx9.color.dcc.independent_64B_blocks && + surf->u.gfx9.color.dcc.max_compressed_block_size == V_028C78_MAX_BLOCK_SIZE_64B)); default: unreachable("unhandled chip"); return false; @@ -1713,12 +1713,12 @@ static int gfx9_compute_miptree(struct ac_addrlib *addrlib, const struct radeon_ } if (in->flags.stencil) { - surf->u.gfx9.stencil_swizzle_mode = in->swizzleMode; - surf->u.gfx9.stencil_epitch = + surf->u.gfx9.zs.stencil_swizzle_mode = in->swizzleMode; + surf->u.gfx9.zs.stencil_epitch = out.epitchIsHeight ? out.mipChainHeight - 1 : out.mipChainPitch - 1; surf->surf_alignment_log2 = MAX2(surf->surf_alignment_log2, util_logbase2(out.baseAlign)); - surf->u.gfx9.stencil_offset = align(surf->surf_size, out.baseAlign); - surf->surf_size = surf->u.gfx9.stencil_offset + out.surfSize; + surf->u.gfx9.zs.stencil_offset = align(surf->surf_size, out.baseAlign); + surf->surf_size = surf->u.gfx9.zs.stencil_offset + out.surfSize; return 0; } @@ -1729,8 +1729,8 @@ static int gfx9_compute_miptree(struct ac_addrlib *addrlib, const struct radeon_ * FMASK only supports the Z swizzle modes, whose numbers are multiples of 4. */ if (!in->flags.depth) { - surf->u.gfx9.fmask_swizzle_mode = surf->u.gfx9.swizzle_mode & ~0x3; - surf->u.gfx9.fmask_epitch = surf->u.gfx9.epitch; + surf->u.gfx9.color.fmask_swizzle_mode = surf->u.gfx9.swizzle_mode & ~0x3; + surf->u.gfx9.color.fmask_epitch = surf->u.gfx9.epitch; } surf->u.gfx9.surf_slice_size = out.sliceSize; @@ -1883,12 +1883,12 @@ static int gfx9_compute_miptree(struct ac_addrlib *addrlib, const struct radeon_ if (ret != ADDR_OK) return ret; - surf->u.gfx9.dcc.rb_aligned = din.dccKeyFlags.rbAligned; - surf->u.gfx9.dcc.pipe_aligned = din.dccKeyFlags.pipeAligned; - surf->u.gfx9.dcc_block_width = dout.compressBlkWidth; - surf->u.gfx9.dcc_block_height = dout.compressBlkHeight; - surf->u.gfx9.dcc_block_depth = dout.compressBlkDepth; - surf->u.gfx9.dcc_pitch_max = dout.pitch - 1; + surf->u.gfx9.color.dcc.rb_aligned = din.dccKeyFlags.rbAligned; + surf->u.gfx9.color.dcc.pipe_aligned = din.dccKeyFlags.pipeAligned; + surf->u.gfx9.color.dcc_block_width = dout.compressBlkWidth; + surf->u.gfx9.color.dcc_block_height = dout.compressBlkHeight; + surf->u.gfx9.color.dcc_block_depth = dout.compressBlkDepth; + surf->u.gfx9.color.dcc_pitch_max = dout.pitch - 1; surf->meta_size = dout.dccRamSize; surf->meta_slice_size = dout.dccRamSliceSize; surf->meta_alignment_log2 = util_logbase2(dout.dccRamBaseAlign); @@ -1938,9 +1938,9 @@ static int gfx9_compute_miptree(struct ac_addrlib *addrlib, const struct radeon_ if (!surf->num_meta_levels) surf->meta_size = 0; - surf->u.gfx9.display_dcc_size = surf->meta_size; - surf->u.gfx9.display_dcc_alignment_log2 = surf->meta_alignment_log2; - surf->u.gfx9.display_dcc_pitch_max = surf->u.gfx9.dcc_pitch_max; + surf->u.gfx9.color.display_dcc_size = surf->meta_size; + surf->u.gfx9.color.display_dcc_alignment_log2 = surf->meta_alignment_log2; + surf->u.gfx9.color.display_dcc_pitch_max = surf->u.gfx9.color.dcc_pitch_max; /* Compute displayable DCC. */ if (((in->flags.display && info->use_display_dcc_with_retile_blit) || @@ -1953,19 +1953,19 @@ static int gfx9_compute_miptree(struct ac_addrlib *addrlib, const struct radeon_ assert(din.numMipLevels == 1); assert(din.numFrags == 1); assert(surf->tile_swizzle == 0); - assert(surf->u.gfx9.dcc.pipe_aligned || surf->u.gfx9.dcc.rb_aligned); + assert(surf->u.gfx9.color.dcc.pipe_aligned || surf->u.gfx9.color.dcc.rb_aligned); ret = Addr2ComputeDccInfo(addrlib->handle, &din, &dout); if (ret != ADDR_OK) return ret; - surf->u.gfx9.display_dcc_size = dout.dccRamSize; - surf->u.gfx9.display_dcc_alignment_log2 = util_logbase2(dout.dccRamBaseAlign); - surf->u.gfx9.display_dcc_pitch_max = dout.pitch - 1; - assert(surf->u.gfx9.display_dcc_size <= surf->meta_size); + surf->u.gfx9.color.display_dcc_size = dout.dccRamSize; + surf->u.gfx9.color.display_dcc_alignment_log2 = util_logbase2(dout.dccRamBaseAlign); + surf->u.gfx9.color.display_dcc_pitch_max = dout.pitch - 1; + assert(surf->u.gfx9.color.display_dcc_size <= surf->meta_size); - surf->u.gfx9.dcc_retile_use_uint16 = - surf->u.gfx9.display_dcc_size <= UINT16_MAX + 1 && surf->meta_size <= UINT16_MAX + 1; + surf->u.gfx9.color.dcc_retile_use_uint16 = + surf->u.gfx9.color.display_dcc_size <= UINT16_MAX + 1 && surf->meta_size <= UINT16_MAX + 1; /* Align the retile map size to get more hash table hits and * decrease the maximum memory footprint when all retile maps @@ -2008,11 +2008,11 @@ static int gfx9_compute_miptree(struct ac_addrlib *addrlib, const struct radeon_ assert(dout.metaBlkWidth >= 128 && dout.metaBlkHeight >= 128); } - surf->u.gfx9.dcc_retile_num_elements = + surf->u.gfx9.color.dcc_retile_num_elements = DIV_ROUND_UP(retile_dim[0], dout.compressBlkWidth) * DIV_ROUND_UP(retile_dim[1], dout.compressBlkHeight) * 2; /* Align the size to 4 (for the compute shader). */ - surf->u.gfx9.dcc_retile_num_elements = align(surf->u.gfx9.dcc_retile_num_elements, 4); + surf->u.gfx9.color.dcc_retile_num_elements = align(surf->u.gfx9.color.dcc_retile_num_elements, 4); /* Compute address mapping from non-displayable to displayable DCC. */ ADDR2_COMPUTE_DCC_ADDRFROMCOORD_INPUT addrin; @@ -2034,11 +2034,11 @@ static int gfx9_compute_miptree(struct ac_addrlib *addrlib, const struct radeon_ addrin.metaBlkDepth = dout.metaBlkDepth; addrin.dccRamSliceSize = 0; /* Don't care for non-layered images. */ - surf->u.gfx9.dcc_retile_map = ac_compute_dcc_retile_map( - addrlib, info, retile_dim[0], retile_dim[1], surf->u.gfx9.dcc.rb_aligned, - surf->u.gfx9.dcc.pipe_aligned, surf->u.gfx9.dcc_retile_use_uint16, - surf->u.gfx9.dcc_retile_num_elements, &addrin); - if (!surf->u.gfx9.dcc_retile_map) + surf->u.gfx9.color.dcc_retile_map = ac_compute_dcc_retile_map( + addrlib, info, retile_dim[0], retile_dim[1], surf->u.gfx9.color.dcc.rb_aligned, + surf->u.gfx9.color.dcc.pipe_aligned, surf->u.gfx9.color.dcc_retile_use_uint16, + surf->u.gfx9.color.dcc_retile_num_elements, &addrin); + if (!surf->u.gfx9.color.dcc_retile_map) return ADDR_OUTOFMEMORY; } } @@ -2065,8 +2065,8 @@ static int gfx9_compute_miptree(struct ac_addrlib *addrlib, const struct radeon_ if (ret != ADDR_OK) return ret; - surf->u.gfx9.fmask_swizzle_mode = fin.swizzleMode; - surf->u.gfx9.fmask_epitch = fout.pitch - 1; + surf->u.gfx9.color.fmask_swizzle_mode = fin.swizzleMode; + surf->u.gfx9.color.fmask_epitch = fout.pitch - 1; surf->fmask_size = fout.fmaskBytes; surf->fmask_alignment_log2 = util_logbase2(fout.baseAlign); surf->fmask_slice_size = fout.sliceSize; @@ -2124,7 +2124,7 @@ static int gfx9_compute_miptree(struct ac_addrlib *addrlib, const struct radeon_ cin.firstMipIdInTail = out.firstMipIdInTail; if (in->numSamples > 1) - cin.swizzleMode = surf->u.gfx9.fmask_swizzle_mode; + cin.swizzleMode = surf->u.gfx9.color.fmask_swizzle_mode; else cin.swizzleMode = in->swizzleMode; @@ -2135,8 +2135,8 @@ static int gfx9_compute_miptree(struct ac_addrlib *addrlib, const struct radeon_ surf->cmask_size = cout.cmaskBytes; surf->cmask_alignment_log2 = util_logbase2(cout.baseAlign); surf->cmask_slice_size = cout.sliceSize; - surf->u.gfx9.cmask_level0.offset = meta_mip_info[0].offset; - surf->u.gfx9.cmask_level0.size = meta_mip_info[0].sliceSize; + surf->u.gfx9.color.cmask_level0.offset = meta_mip_info[0].offset; + surf->u.gfx9.color.cmask_level0.size = meta_mip_info[0].sliceSize; } } @@ -2245,13 +2245,13 @@ static int gfx9_compute_surface(struct ac_addrlib *addrlib, const struct radeon_ } else if (!AddrSurfInfoIn.flags.depth && !AddrSurfInfoIn.flags.stencil) { /* Optimal values for the L2 cache. */ if (info->chip_class == GFX9) { - surf->u.gfx9.dcc.independent_64B_blocks = 1; - surf->u.gfx9.dcc.independent_128B_blocks = 0; - surf->u.gfx9.dcc.max_compressed_block_size = V_028C78_MAX_BLOCK_SIZE_64B; + surf->u.gfx9.color.dcc.independent_64B_blocks = 1; + surf->u.gfx9.color.dcc.independent_128B_blocks = 0; + surf->u.gfx9.color.dcc.max_compressed_block_size = V_028C78_MAX_BLOCK_SIZE_64B; } else if (info->chip_class >= GFX10) { - surf->u.gfx9.dcc.independent_64B_blocks = 0; - surf->u.gfx9.dcc.independent_128B_blocks = 1; - surf->u.gfx9.dcc.max_compressed_block_size = V_028C78_MAX_BLOCK_SIZE_128B; + surf->u.gfx9.color.dcc.independent_64B_blocks = 0; + surf->u.gfx9.color.dcc.independent_128B_blocks = 1; + surf->u.gfx9.color.dcc.max_compressed_block_size = V_028C78_MAX_BLOCK_SIZE_128B; } if (AddrSurfInfoIn.flags.display) { @@ -2273,15 +2273,15 @@ static int gfx9_compute_surface(struct ac_addrlib *addrlib, const struct radeon_ * but without DCC image stores. */ if (info->family == CHIP_NAVI12 || info->family == CHIP_NAVI14) { - surf->u.gfx9.dcc.independent_64B_blocks = 1; - surf->u.gfx9.dcc.independent_128B_blocks = 0; - surf->u.gfx9.dcc.max_compressed_block_size = V_028C78_MAX_BLOCK_SIZE_64B; + surf->u.gfx9.color.dcc.independent_64B_blocks = 1; + surf->u.gfx9.color.dcc.independent_128B_blocks = 0; + surf->u.gfx9.color.dcc.max_compressed_block_size = V_028C78_MAX_BLOCK_SIZE_64B; } if (info->chip_class >= GFX10_3) { - surf->u.gfx9.dcc.independent_64B_blocks = 1; - surf->u.gfx9.dcc.independent_128B_blocks = 1; - surf->u.gfx9.dcc.max_compressed_block_size = V_028C78_MAX_BLOCK_SIZE_64B; + surf->u.gfx9.color.dcc.independent_64B_blocks = 1; + surf->u.gfx9.color.dcc.independent_128B_blocks = 1; + surf->u.gfx9.color.dcc.max_compressed_block_size = V_028C78_MAX_BLOCK_SIZE_64B; } } } @@ -2332,11 +2332,11 @@ static int gfx9_compute_surface(struct ac_addrlib *addrlib, const struct radeon_ surf->meta_slice_size = 0; surf->u.gfx9.surf_offset = 0; if (AddrSurfInfoIn.flags.stencil) - surf->u.gfx9.stencil_offset = 0; + surf->u.gfx9.zs.stencil_offset = 0; surf->cmask_size = 0; - surf->u.gfx9.dcc_retile_use_uint16 = false; - surf->u.gfx9.dcc_retile_num_elements = 0; - surf->u.gfx9.dcc_retile_map = NULL; + surf->u.gfx9.color.dcc_retile_use_uint16 = false; + surf->u.gfx9.color.dcc_retile_num_elements = 0; + surf->u.gfx9.color.dcc_retile_map = NULL; const bool only_stencil = (surf->flags & RADEON_SURF_SBUFFER) && !(surf->flags & RADEON_SURF_ZBUFFER); @@ -2381,10 +2381,10 @@ static int gfx9_compute_surface(struct ac_addrlib *addrlib, const struct radeon_ /* Display needs unaligned DCC. */ if (!(surf->flags & RADEON_SURF_Z_OR_SBUFFER) && surf->num_meta_levels && - (!is_dcc_supported_by_DCN(info, config, surf, surf->u.gfx9.dcc.rb_aligned, - surf->u.gfx9.dcc.pipe_aligned) || + (!is_dcc_supported_by_DCN(info, config, surf, surf->u.gfx9.color.dcc.rb_aligned, + surf->u.gfx9.color.dcc.pipe_aligned) || /* Don't set is_displayable if displayable DCC is missing. */ - (info->use_display_dcc_with_retile_blit && !surf->u.gfx9.dcc_retile_num_elements))) + (info->use_display_dcc_with_retile_blit && !surf->u.gfx9.color.dcc_retile_num_elements))) displayable = false; } surf->is_displayable = displayable; @@ -2398,8 +2398,8 @@ static int gfx9_compute_surface(struct ac_addrlib *addrlib, const struct radeon_ if (AddrSurfInfoIn.flags.color) assert(is_dcc_supported_by_CB(info, surf->u.gfx9.swizzle_mode)); if (AddrSurfInfoIn.flags.display) { - assert(is_dcc_supported_by_DCN(info, config, surf, surf->u.gfx9.dcc.rb_aligned, - surf->u.gfx9.dcc.pipe_aligned)); + assert(is_dcc_supported_by_DCN(info, config, surf, surf->u.gfx9.color.dcc.rb_aligned, + surf->u.gfx9.color.dcc.pipe_aligned)); } } @@ -2530,10 +2530,10 @@ int ac_compute_surface(struct ac_addrlib *addrlib, const struct radeon_info *inf * the image due to hw-specific reasons. */ if (!(surf->flags & RADEON_SURF_Z_OR_SBUFFER) && - info->chip_class >= GFX9 && surf->u.gfx9.dcc_retile_num_elements) { + info->chip_class >= GFX9 && surf->u.gfx9.color.dcc_retile_num_elements) { /* Add space for the displayable DCC buffer. */ - surf->display_dcc_offset = align64(surf->total_size, 1 << surf->u.gfx9.display_dcc_alignment_log2); - surf->total_size = surf->display_dcc_offset + surf->u.gfx9.display_dcc_size; + surf->display_dcc_offset = align64(surf->total_size, 1 << surf->u.gfx9.color.display_dcc_alignment_log2); + surf->total_size = surf->display_dcc_offset + surf->u.gfx9.color.display_dcc_size; } surf->meta_offset = align64(surf->total_size, 1 << surf->meta_alignment_log2); @@ -2619,13 +2619,13 @@ void ac_surface_set_bo_metadata(const struct radeon_info *info, struct radeon_su if (info->chip_class >= GFX9) { surf->u.gfx9.swizzle_mode = AMDGPU_TILING_GET(tiling_flags, SWIZZLE_MODE); - surf->u.gfx9.dcc.independent_64B_blocks = + surf->u.gfx9.color.dcc.independent_64B_blocks = AMDGPU_TILING_GET(tiling_flags, DCC_INDEPENDENT_64B); - surf->u.gfx9.dcc.independent_128B_blocks = + surf->u.gfx9.color.dcc.independent_128B_blocks = AMDGPU_TILING_GET(tiling_flags, DCC_INDEPENDENT_128B); - surf->u.gfx9.dcc.max_compressed_block_size = + surf->u.gfx9.color.dcc.max_compressed_block_size = AMDGPU_TILING_GET(tiling_flags, DCC_MAX_COMPRESSED_BLOCK_SIZE); - surf->u.gfx9.display_dcc_pitch_max = AMDGPU_TILING_GET(tiling_flags, DCC_PITCH_MAX); + surf->u.gfx9.color.display_dcc_pitch_max = AMDGPU_TILING_GET(tiling_flags, DCC_PITCH_MAX); scanout = AMDGPU_TILING_GET(tiling_flags, SCANOUT); *mode = surf->u.gfx9.swizzle_mode > 0 ? RADEON_SURF_MODE_2D : RADEON_SURF_MODE_LINEAR_ALIGNED; @@ -2667,13 +2667,13 @@ void ac_surface_get_bo_metadata(const struct radeon_info *info, struct radeon_su *tiling_flags |= AMDGPU_TILING_SET(SWIZZLE_MODE, surf->u.gfx9.swizzle_mode); *tiling_flags |= AMDGPU_TILING_SET(DCC_OFFSET_256B, dcc_offset >> 8); - *tiling_flags |= AMDGPU_TILING_SET(DCC_PITCH_MAX, surf->u.gfx9.display_dcc_pitch_max); + *tiling_flags |= AMDGPU_TILING_SET(DCC_PITCH_MAX, surf->u.gfx9.color.display_dcc_pitch_max); *tiling_flags |= - AMDGPU_TILING_SET(DCC_INDEPENDENT_64B, surf->u.gfx9.dcc.independent_64B_blocks); + AMDGPU_TILING_SET(DCC_INDEPENDENT_64B, surf->u.gfx9.color.dcc.independent_64B_blocks); *tiling_flags |= - AMDGPU_TILING_SET(DCC_INDEPENDENT_128B, surf->u.gfx9.dcc.independent_128B_blocks); + AMDGPU_TILING_SET(DCC_INDEPENDENT_128B, surf->u.gfx9.color.dcc.independent_128B_blocks); *tiling_flags |= AMDGPU_TILING_SET(DCC_MAX_COMPRESSED_BLOCK_SIZE, - surf->u.gfx9.dcc.max_compressed_block_size); + surf->u.gfx9.color.dcc.max_compressed_block_size); *tiling_flags |= AMDGPU_TILING_SET(SCANOUT, (surf->flags & RADEON_SURF_SCANOUT) != 0); } else { if (surf->u.legacy.level[0].mode >= RADEON_SURF_MODE_2D) @@ -2767,11 +2767,11 @@ bool ac_surface_set_umd_metadata(const struct radeon_info *info, struct radeon_s case GFX9: surf->meta_offset = ((uint64_t)desc[7] << 8) | ((uint64_t)G_008F24_META_DATA_ADDRESS(desc[5]) << 40); - surf->u.gfx9.dcc.pipe_aligned = G_008F24_META_PIPE_ALIGNED(desc[5]); - surf->u.gfx9.dcc.rb_aligned = G_008F24_META_RB_ALIGNED(desc[5]); + surf->u.gfx9.color.dcc.pipe_aligned = G_008F24_META_PIPE_ALIGNED(desc[5]); + surf->u.gfx9.color.dcc.rb_aligned = G_008F24_META_RB_ALIGNED(desc[5]); /* If DCC is unaligned, this can only be a displayable image. */ - if (!surf->u.gfx9.dcc.pipe_aligned && !surf->u.gfx9.dcc.rb_aligned) + if (!surf->u.gfx9.color.dcc.pipe_aligned && !surf->u.gfx9.color.dcc.rb_aligned) assert(surf->is_displayable); break; @@ -2779,7 +2779,7 @@ bool ac_surface_set_umd_metadata(const struct radeon_info *info, struct radeon_s case GFX10_3: surf->meta_offset = ((uint64_t)G_00A018_META_DATA_ADDRESS_LO(desc[6]) << 8) | ((uint64_t)desc[7] << 16); - surf->u.gfx9.dcc.pipe_aligned = G_00A018_META_PIPE_ALIGNED(desc[6]); + surf->u.gfx9.color.dcc.pipe_aligned = G_00A018_META_PIPE_ALIGNED(desc[6]); break; default: @@ -2910,8 +2910,8 @@ bool ac_surface_override_offset_stride(const struct radeon_info *info, struct ra } } surf->u.gfx9.surf_offset = offset; - if (surf->u.gfx9.stencil_offset) - surf->u.gfx9.stencil_offset += offset; + if (surf->u.gfx9.zs.stencil_offset) + surf->u.gfx9.zs.stencil_offset += offset; } else { if (pitch) { if (surf->u.legacy.level[0].nblk_x != pitch && require_equal_pitch) @@ -2993,9 +2993,9 @@ uint64_t ac_surface_get_plane_stride(enum chip_class chip_class, } case 1: return 1 + (surf->display_dcc_offset ? - surf->u.gfx9.display_dcc_pitch_max : surf->u.gfx9.dcc_pitch_max); + surf->u.gfx9.color.display_dcc_pitch_max : surf->u.gfx9.color.dcc_pitch_max); case 2: - return surf->u.gfx9.dcc_pitch_max + 1; + return surf->u.gfx9.color.dcc_pitch_max + 1; default: unreachable("Invalid plane index"); } @@ -3009,7 +3009,7 @@ uint64_t ac_surface_get_plane_size(const struct radeon_surf *surf, return surf->surf_size; case 1: return surf->display_dcc_offset ? - surf->u.gfx9.display_dcc_size : surf->meta_size; + surf->u.gfx9.color.display_dcc_size : surf->meta_size; case 2: return surf->meta_size; default: @@ -3019,8 +3019,8 @@ uint64_t ac_surface_get_plane_size(const struct radeon_surf *surf, uint32_t ac_surface_get_retile_map_size(const struct radeon_surf *surf) { - return surf->u.gfx9.dcc_retile_num_elements * - (surf->u.gfx9.dcc_retile_use_uint16 ? 2 : 4); + return surf->u.gfx9.color.dcc_retile_num_elements * + (surf->u.gfx9.color.dcc_retile_use_uint16 ? 2 : 4); } void ac_surface_print_info(FILE *out, const struct radeon_info *info, @@ -3041,8 +3041,8 @@ void ac_surface_print_info(FILE *out, const struct radeon_info *info, " FMask: offset=%" PRIu64 ", size=%" PRIu64 ", " "alignment=%u, swmode=%u, epitch=%u\n", surf->fmask_offset, surf->fmask_size, - 1 << surf->fmask_alignment_log2, surf->u.gfx9.fmask_swizzle_mode, - surf->u.gfx9.fmask_epitch); + 1 << surf->fmask_alignment_log2, surf->u.gfx9.color.fmask_swizzle_mode, + surf->u.gfx9.color.fmask_epitch); if (surf->cmask_offset) fprintf(out, @@ -3062,14 +3062,14 @@ void ac_surface_print_info(FILE *out, const struct radeon_info *info, " DCC: offset=%" PRIu64 ", size=%u, " "alignment=%u, pitch_max=%u, num_dcc_levels=%u\n", surf->meta_offset, surf->meta_size, 1 << surf->meta_alignment_log2, - surf->u.gfx9.display_dcc_pitch_max, surf->num_meta_levels); + surf->u.gfx9.color.display_dcc_pitch_max, surf->num_meta_levels); - if (surf->u.gfx9.stencil_offset) + if (surf->u.gfx9.zs.stencil_offset) fprintf(out, " Stencil: offset=%" PRIu64 ", swmode=%u, epitch=%u\n", - surf->u.gfx9.stencil_offset, - surf->u.gfx9.stencil_swizzle_mode, - surf->u.gfx9.stencil_epitch); + surf->u.gfx9.zs.stencil_offset, + surf->u.gfx9.zs.stencil_swizzle_mode, + surf->u.gfx9.zs.stencil_epitch); } else { fprintf(out, " Surf: size=%" PRIu64 ", alignment=%u, blk_w=%u, blk_h=%u, " @@ -3092,17 +3092,17 @@ void ac_surface_print_info(FILE *out, const struct radeon_info *info, "alignment=%u, pitch_in_pixels=%u, bankh=%u, " "slice_tile_max=%u, tile_mode_index=%u\n", surf->fmask_offset, surf->fmask_size, - 1 << surf->fmask_alignment_log2, surf->u.legacy.fmask.pitch_in_pixels, - surf->u.legacy.fmask.bankh, - surf->u.legacy.fmask.slice_tile_max, - surf->u.legacy.fmask.tiling_index); + 1 << surf->fmask_alignment_log2, surf->u.legacy.color.fmask.pitch_in_pixels, + surf->u.legacy.color.fmask.bankh, + surf->u.legacy.color.fmask.slice_tile_max, + surf->u.legacy.color.fmask.tiling_index); if (surf->cmask_offset) fprintf(out, " CMask: offset=%" PRIu64 ", size=%u, alignment=%u, " "slice_tile_max=%u\n", surf->cmask_offset, surf->cmask_size, - 1 << surf->cmask_alignment_log2, surf->u.legacy.cmask_slice_tile_max); + 1 << surf->cmask_alignment_log2, surf->u.legacy.color.cmask_slice_tile_max); if (surf->flags & RADEON_SURF_Z_OR_SBUFFER && surf->meta_offset) fprintf(out, " HTile: offset=%" PRIu64 ", size=%u, alignment=%u\n", diff --git a/src/amd/common/ac_surface.h b/src/amd/common/ac_surface.h index b574f2ce2e4..1679ef9401d 100644 --- a/src/amd/common/ac_surface.h +++ b/src/amd/common/ac_surface.h @@ -132,13 +132,13 @@ struct legacy_surf_layout { struct legacy_surf_dcc_level dcc_level[RADEON_SURF_MAX_LEVELS]; struct legacy_surf_fmask fmask; unsigned cmask_slice_tile_max; - }; + } color; /* Z/S layout */ struct { struct legacy_surf_level stencil_level[RADEON_SURF_MAX_LEVELS]; uint8_t stencil_tiling_index[RADEON_SURF_MAX_LEVELS]; - }; + } zs; }; }; @@ -220,14 +220,14 @@ struct gfx9_surf_layout { /* CMASK level info (only level 0) */ struct gfx9_surf_level cmask_level0; - }; + } color; /* Z/S */ struct { uint64_t stencil_offset; /* separate stencil */ uint16_t stencil_epitch; /* gfx9 only, not on gfx10 */ uint8_t stencil_swizzle_mode; - }; + } zs; }; }; diff --git a/src/amd/common/ac_surface_modifier_test.c b/src/amd/common/ac_surface_modifier_test.c index 5b74fa07728..b6acd6cfe7b 100644 --- a/src/amd/common/ac_surface_modifier_test.c +++ b/src/amd/common/ac_surface_modifier_test.c @@ -83,8 +83,8 @@ get_addr_from_coord_base(ADDR_HANDLE addrlib, const struct radeon_surf *surf, din.numSlices = 1; din.numMipLevels = 1; din.numFrags = 1; - din.dccKeyFlags.pipeAligned = surf->u.gfx9.dcc.pipe_aligned; - din.dccKeyFlags.rbAligned = surf->u.gfx9.dcc.rb_aligned; + din.dccKeyFlags.pipeAligned = surf->u.gfx9.color.dcc.pipe_aligned; + din.dccKeyFlags.rbAligned = surf->u.gfx9.color.dcc.rb_aligned; din.dataSurfaceSize = surf->surf_size; ADDR_E_RETURNCODE ret = Addr2ComputeDccInfo(addrlib, &din, &dout); @@ -125,8 +125,8 @@ void generate_hash(struct ac_addrlib *ac_addrlib, _mesa_sha1_update(&ctx, &surf->total_size, sizeof(surf->total_size)); _mesa_sha1_update(&ctx, &surf->meta_offset, sizeof(surf->meta_offset)); _mesa_sha1_update(&ctx, &surf->display_dcc_offset, sizeof(surf->display_dcc_offset)); - _mesa_sha1_update(&ctx, &surf->u.gfx9.display_dcc_pitch_max, - sizeof(surf->u.gfx9.display_dcc_pitch_max)); + _mesa_sha1_update(&ctx, &surf->u.gfx9.color.display_dcc_pitch_max, + sizeof(surf->u.gfx9.color.display_dcc_pitch_max)); ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_INPUT input = {0}; input.size = sizeof(input); @@ -145,8 +145,8 @@ void generate_hash(struct ac_addrlib *ac_addrlib, if (surf->meta_offset) { dcc_input = get_addr_from_coord_base(addrlib, surf, entry->w, entry->h, entry->format, - surf->u.gfx9.dcc.rb_aligned, - surf->u.gfx9.dcc.pipe_aligned); + surf->u.gfx9.color.dcc.rb_aligned, + surf->u.gfx9.color.dcc.pipe_aligned); } ADDR2_COMPUTE_DCC_ADDRFROMCOORD_INPUT display_dcc_input = {0}; @@ -283,8 +283,8 @@ static void test_modifier(const struct radeon_info *info, elem_bits, 20, &dcc_pitch, NULL) << 12; - assert(surf.u.gfx9.display_dcc_size == align(dcc_size, dcc_align)); - assert(surf.u.gfx9.display_dcc_pitch_max + 1 == dcc_pitch); + assert(surf.u.gfx9.color.display_dcc_size == align(dcc_size, dcc_align)); + assert(surf.u.gfx9.color.display_dcc_pitch_max + 1 == dcc_pitch); assert(surf.display_dcc_offset == expected_offset); expected_offset += align(dcc_size, dcc_align); diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c index bcc604f74ad..660f5139a32 100644 --- a/src/amd/vulkan/radv_cmd_buffer.c +++ b/src/amd/vulkan/radv_cmd_buffer.c @@ -5906,7 +5906,7 @@ radv_init_dcc(struct radv_cmd_buffer *cmd_buffer, struct radv_image *image, */ /* Compute the size of all fast clearable DCC levels. */ for (unsigned i = 0; i < image->planes[0].surface.num_meta_levels; i++) { - struct legacy_surf_dcc_level *dcc_level = &image->planes[0].surface.u.legacy.dcc_level[i]; + struct legacy_surf_dcc_level *dcc_level = &image->planes[0].surface.u.legacy.color.dcc_level[i]; unsigned dcc_fast_clear_size = dcc_level->dcc_slice_fast_clear_size * image->info.array_size; diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c index fa485c6089e..02191d22a1f 100644 --- a/src/amd/vulkan/radv_device.c +++ b/src/amd/vulkan/radv_device.c @@ -6185,7 +6185,7 @@ static inline unsigned si_tile_mode_index(const struct radv_image_plane *plane, unsigned level, bool stencil) { if (stencil) - return plane->surface.u.legacy.stencil_tiling_index[level]; + return plane->surface.u.legacy.zs.stencil_tiling_index[level]; else return plane->surface.u.legacy.tiling_index[level]; } @@ -6242,9 +6242,9 @@ radv_init_dcc_control_reg(struct radv_device *device, struct radv_image_view *iv * and max_uncompressed) */ if (device->physical_device->rad_info.chip_class >= GFX9) { max_compressed_block_size = - iview->image->planes[0].surface.u.gfx9.dcc.max_compressed_block_size; - independent_128b_blocks = iview->image->planes[0].surface.u.gfx9.dcc.independent_128B_blocks; - independent_64b_blocks = iview->image->planes[0].surface.u.gfx9.dcc.independent_64B_blocks; + iview->image->planes[0].surface.u.gfx9.color.dcc.max_compressed_block_size; + independent_128b_blocks = iview->image->planes[0].surface.u.gfx9.color.dcc.independent_128B_blocks; + independent_64b_blocks = iview->image->planes[0].surface.u.gfx9.color.dcc.independent_64B_blocks; } else { independent_128b_blocks = 0; @@ -6297,9 +6297,9 @@ radv_initialise_color_surface(struct radv_device *device, struct radv_color_buff if (device->physical_device->rad_info.chip_class >= GFX9) { if (device->physical_device->rad_info.chip_class >= GFX10) { cb->cb_color_attrib3 |= S_028EE0_COLOR_SW_MODE(surf->u.gfx9.swizzle_mode) | - S_028EE0_FMASK_SW_MODE(surf->u.gfx9.fmask_swizzle_mode) | + S_028EE0_FMASK_SW_MODE(surf->u.gfx9.color.fmask_swizzle_mode) | S_028EE0_CMASK_PIPE_ALIGNED(1) | - S_028EE0_DCC_PIPE_ALIGNED(surf->u.gfx9.dcc.pipe_aligned); + S_028EE0_DCC_PIPE_ALIGNED(surf->u.gfx9.color.dcc.pipe_aligned); } else { struct gfx9_surf_meta_flags meta = { .rb_aligned = 1, @@ -6307,10 +6307,10 @@ radv_initialise_color_surface(struct radv_device *device, struct radv_color_buff }; if (surf->meta_offset) - meta = surf->u.gfx9.dcc; + meta = surf->u.gfx9.color.dcc; cb->cb_color_attrib |= S_028C74_COLOR_SW_MODE(surf->u.gfx9.swizzle_mode) | - S_028C74_FMASK_SW_MODE(surf->u.gfx9.fmask_swizzle_mode) | + S_028C74_FMASK_SW_MODE(surf->u.gfx9.color.fmask_swizzle_mode) | S_028C74_RB_ALIGNED(meta.rb_aligned) | S_028C74_PIPE_ALIGNED(meta.pipe_aligned); cb->cb_mrt_epitch = S_0287A0_EPITCH(surf->u.gfx9.epitch); @@ -6332,16 +6332,16 @@ radv_initialise_color_surface(struct radv_device *device, struct radv_color_buff cb->cb_color_pitch = S_028C64_TILE_MAX(pitch_tile_max); cb->cb_color_slice = S_028C68_TILE_MAX(slice_tile_max); - cb->cb_color_cmask_slice = surf->u.legacy.cmask_slice_tile_max; + cb->cb_color_cmask_slice = surf->u.legacy.color.cmask_slice_tile_max; cb->cb_color_attrib |= S_028C74_TILE_MODE_INDEX(tile_mode_index); if (radv_image_has_fmask(iview->image)) { if (device->physical_device->rad_info.chip_class >= GFX7) cb->cb_color_pitch |= - S_028C64_FMASK_TILE_MAX(surf->u.legacy.fmask.pitch_in_pixels / 8 - 1); - cb->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(surf->u.legacy.fmask.tiling_index); - cb->cb_color_fmask_slice = S_028C88_TILE_MAX(surf->u.legacy.fmask.slice_tile_max); + S_028C64_FMASK_TILE_MAX(surf->u.legacy.color.fmask.pitch_in_pixels / 8 - 1); + cb->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(surf->u.legacy.color.fmask.tiling_index); + cb->cb_color_fmask_slice = S_028C88_TILE_MAX(surf->u.legacy.color.fmask.slice_tile_max); } else { /* This must be set for fast clear to work without FMASK. */ if (device->physical_device->rad_info.chip_class >= GFX7) @@ -6361,7 +6361,7 @@ radv_initialise_color_surface(struct radv_device *device, struct radv_color_buff if (radv_dcc_enabled(iview->image, iview->base_mip) && device->physical_device->rad_info.chip_class <= GFX8) - va += plane->surface.u.legacy.dcc_level[iview->base_mip].dcc_offset; + va += plane->surface.u.legacy.color.dcc_level[iview->base_mip].dcc_offset; unsigned dcc_tile_swizzle = surf->tile_swizzle; dcc_tile_swizzle &= ((1 << surf->meta_alignment_log2) - 1) >> 8; @@ -6427,7 +6427,7 @@ radv_initialise_color_surface(struct radv_device *device, struct radv_color_buff if (radv_image_has_fmask(iview->image)) { cb->cb_color_info |= S_028C70_COMPRESSION(1); if (device->physical_device->rad_info.chip_class == GFX6) { - unsigned fmask_bankh = util_logbase2(surf->u.legacy.fmask.bankh); + unsigned fmask_bankh = util_logbase2(surf->u.legacy.color.fmask.bankh); cb->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(fmask_bankh); } @@ -6580,18 +6580,18 @@ radv_initialise_ds_surface(struct radv_device *device, struct radv_ds_buffer_inf if (device->physical_device->rad_info.chip_class >= GFX9) { assert(surf->u.gfx9.surf_offset == 0); - s_offs += surf->u.gfx9.stencil_offset; + s_offs += surf->u.gfx9.zs.stencil_offset; ds->db_z_info = S_028038_FORMAT(format) | S_028038_NUM_SAMPLES(util_logbase2(iview->image->info.samples)) | S_028038_SW_MODE(surf->u.gfx9.swizzle_mode) | S_028038_MAXMIP(iview->image->info.levels - 1) | S_028038_ZRANGE_PRECISION(1); ds->db_stencil_info = - S_02803C_FORMAT(stencil_format) | S_02803C_SW_MODE(surf->u.gfx9.stencil_swizzle_mode); + S_02803C_FORMAT(stencil_format) | S_02803C_SW_MODE(surf->u.gfx9.zs.stencil_swizzle_mode); if (device->physical_device->rad_info.chip_class == GFX9) { ds->db_z_info2 = S_028068_EPITCH(surf->u.gfx9.epitch); - ds->db_stencil_info2 = S_02806C_EPITCH(surf->u.gfx9.stencil_epitch); + ds->db_stencil_info2 = S_02806C_EPITCH(surf->u.gfx9.zs.stencil_epitch); } ds->db_depth_view |= S_028008_MIPID(level); @@ -6631,10 +6631,10 @@ radv_initialise_ds_surface(struct radv_device *device, struct radv_ds_buffer_inf const struct legacy_surf_level *level_info = &surf->u.legacy.level[level]; if (stencil_only) - level_info = &surf->u.legacy.stencil_level[level]; + level_info = &surf->u.legacy.zs.stencil_level[level]; z_offs += (uint64_t)surf->u.legacy.level[level].offset_256B * 256; - s_offs += (uint64_t)surf->u.legacy.stencil_level[level].offset_256B * 256; + s_offs += (uint64_t)surf->u.legacy.zs.stencil_level[level].offset_256B * 256; ds->db_depth_info = S_02803C_ADDR5_SWIZZLE_MASK(!radv_image_is_tc_compat_htile(iview->image)); ds->db_z_info = S_028040_FORMAT(format) | S_028040_ZRANGE_PRECISION(1); @@ -6646,7 +6646,7 @@ radv_initialise_ds_surface(struct radv_device *device, struct radv_ds_buffer_inf if (device->physical_device->rad_info.chip_class >= GFX7) { struct radeon_info *info = &device->physical_device->rad_info; unsigned tiling_index = surf->u.legacy.tiling_index[level]; - unsigned stencil_index = surf->u.legacy.stencil_tiling_index[level]; + unsigned stencil_index = surf->u.legacy.zs.stencil_tiling_index[level]; unsigned macro_index = surf->u.legacy.macro_tile_index; unsigned tile_mode = info->si_tile_mode_array[tiling_index]; unsigned stencil_tile_mode = info->si_tile_mode_array[stencil_index]; diff --git a/src/amd/vulkan/radv_image.c b/src/amd/vulkan/radv_image.c index 650f8ecdef7..bcc8f5768fe 100644 --- a/src/amd/vulkan/radv_image.c +++ b/src/amd/vulkan/radv_image.c @@ -561,7 +561,7 @@ static inline unsigned si_tile_mode_index(const struct radv_image_plane *plane, unsigned level, bool stencil) { if (stencil) - return plane->surface.u.legacy.stencil_tiling_index[level]; + return plane->surface.u.legacy.zs.stencil_tiling_index[level]; else return plane->surface.u.legacy.tiling_index[level]; } @@ -684,7 +684,7 @@ si_set_mutable_tex_desc_fields(struct radv_device *device, struct radv_image *im uint64_t meta_va = 0; if (chip_class >= GFX9) { if (is_stencil) - va += plane->surface.u.gfx9.stencil_offset; + va += plane->surface.u.gfx9.zs.stencil_offset; else va += plane->surface.u.gfx9.surf_offset; } else @@ -702,7 +702,7 @@ si_set_mutable_tex_desc_fields(struct radv_device *device, struct radv_image *im if (!disable_compression && radv_dcc_enabled(image, first_level)) { meta_va = gpu_address + plane->surface.meta_offset; if (chip_class <= GFX8) - meta_va += plane->surface.u.legacy.dcc_level[base_level].dcc_offset; + meta_va += plane->surface.u.legacy.color.dcc_level[base_level].dcc_offset; unsigned dcc_tile_swizzle = plane->surface.tile_swizzle << 8; dcc_tile_swizzle &= (1 << plane->surface.meta_alignment_log2) - 1; @@ -722,7 +722,7 @@ si_set_mutable_tex_desc_fields(struct radv_device *device, struct radv_image *im state[3] &= C_00A00C_SW_MODE; if (is_stencil) { - state[3] |= S_00A00C_SW_MODE(plane->surface.u.gfx9.stencil_swizzle_mode); + state[3] |= S_00A00C_SW_MODE(plane->surface.u.gfx9.zs.stencil_swizzle_mode); } else { state[3] |= S_00A00C_SW_MODE(plane->surface.u.gfx9.swizzle_mode); } @@ -736,7 +736,7 @@ si_set_mutable_tex_desc_fields(struct radv_device *device, struct radv_image *im }; if (!(plane->surface.flags & RADEON_SURF_Z_OR_SBUFFER)) - meta = plane->surface.u.gfx9.dcc; + meta = plane->surface.u.gfx9.color.dcc; if (radv_dcc_enabled(image, first_level) && is_storage_image && enable_write_compression) state[6] |= S_00A018_WRITE_COMPRESS_ENABLE(1); @@ -751,8 +751,8 @@ si_set_mutable_tex_desc_fields(struct radv_device *device, struct radv_image *im state[4] &= C_008F20_PITCH; if (is_stencil) { - state[3] |= S_008F1C_SW_MODE(plane->surface.u.gfx9.stencil_swizzle_mode); - state[4] |= S_008F20_PITCH(plane->surface.u.gfx9.stencil_epitch); + state[3] |= S_008F1C_SW_MODE(plane->surface.u.gfx9.zs.stencil_swizzle_mode); + state[4] |= S_008F20_PITCH(plane->surface.u.gfx9.zs.stencil_epitch); } else { state[3] |= S_008F1C_SW_MODE(plane->surface.u.gfx9.swizzle_mode); state[4] |= S_008F20_PITCH(plane->surface.u.gfx9.epitch); @@ -767,7 +767,7 @@ si_set_mutable_tex_desc_fields(struct radv_device *device, struct radv_image *im }; if (!(plane->surface.flags & RADEON_SURF_Z_OR_SBUFFER)) - meta = plane->surface.u.gfx9.dcc; + meta = plane->surface.u.gfx9.color.dcc; state[5] |= S_008F24_META_DATA_ADDRESS(meta_va >> 40) | S_008F24_META_PIPE_ALIGNED(meta.pipe_aligned) | @@ -912,7 +912,7 @@ gfx10_make_texture_descriptor(struct radv_device *device, struct radv_image *ima if (radv_dcc_enabled(image, first_level)) { state[6] |= S_00A018_MAX_UNCOMPRESSED_BLOCK_SIZE(V_028C78_MAX_BLOCK_SIZE_256B) | S_00A018_MAX_COMPRESSED_BLOCK_SIZE( - image->planes[0].surface.u.gfx9.dcc.max_compressed_block_size) | + image->planes[0].surface.u.gfx9.color.dcc.max_compressed_block_size) | S_00A018_ALPHA_IS_ON_MSB(vi_alpha_is_on_msb(device, vk_format)); } @@ -949,7 +949,7 @@ gfx10_make_texture_descriptor(struct radv_device *device, struct radv_image *ima fmask_state[3] = S_00A00C_DST_SEL_X(V_008F1C_SQ_SEL_X) | S_00A00C_DST_SEL_Y(V_008F1C_SQ_SEL_X) | S_00A00C_DST_SEL_Z(V_008F1C_SQ_SEL_X) | S_00A00C_DST_SEL_W(V_008F1C_SQ_SEL_X) | - S_00A00C_SW_MODE(image->planes[0].surface.u.gfx9.fmask_swizzle_mode) | + S_00A00C_SW_MODE(image->planes[0].surface.u.gfx9.color.fmask_swizzle_mode) | S_00A00C_TYPE( radv_tex_dim(image->type, view_type, image->info.array_size, 0, false, false)); fmask_state[4] = S_00A010_DEPTH(last_layer) | S_00A010_BASE_ARRAY(first_layer); @@ -1130,9 +1130,9 @@ si_make_texture_descriptor(struct radv_device *device, struct radv_image *image, fmask_state[7] = 0; if (device->physical_device->rad_info.chip_class == GFX9) { - fmask_state[3] |= S_008F1C_SW_MODE(image->planes[0].surface.u.gfx9.fmask_swizzle_mode); + fmask_state[3] |= S_008F1C_SW_MODE(image->planes[0].surface.u.gfx9.color.fmask_swizzle_mode); fmask_state[4] |= S_008F20_DEPTH(last_layer) | - S_008F20_PITCH(image->planes[0].surface.u.gfx9.fmask_epitch); + S_008F20_PITCH(image->planes[0].surface.u.gfx9.color.fmask_epitch); fmask_state[5] |= S_008F24_META_PIPE_ALIGNED(1) | S_008F24_META_RB_ALIGNED(1); if (radv_image_is_tc_compat_cmask(image)) { @@ -1144,10 +1144,10 @@ si_make_texture_descriptor(struct radv_device *device, struct radv_image *image, } } else { fmask_state[3] |= - S_008F1C_TILING_INDEX(image->planes[0].surface.u.legacy.fmask.tiling_index); + S_008F1C_TILING_INDEX(image->planes[0].surface.u.legacy.color.fmask.tiling_index); fmask_state[4] |= S_008F20_DEPTH(depth - 1) | - S_008F20_PITCH(image->planes[0].surface.u.legacy.fmask.pitch_in_pixels - 1); + S_008F20_PITCH(image->planes[0].surface.u.legacy.color.fmask.pitch_in_pixels - 1); fmask_state[5] |= S_008F24_LAST_ARRAY(last_layer); if (radv_image_is_tc_compat_cmask(image)) { @@ -1217,11 +1217,11 @@ radv_init_metadata(struct radv_device *device, struct radv_image *image, (surface->display_dcc_offset ? surface->display_dcc_offset : surface->meta_offset); metadata->u.gfx9.swizzle_mode = surface->u.gfx9.swizzle_mode; metadata->u.gfx9.dcc_offset_256b = dcc_offset >> 8; - metadata->u.gfx9.dcc_pitch_max = surface->u.gfx9.display_dcc_pitch_max; - metadata->u.gfx9.dcc_independent_64b_blocks = surface->u.gfx9.dcc.independent_64B_blocks; - metadata->u.gfx9.dcc_independent_128b_blocks = surface->u.gfx9.dcc.independent_128B_blocks; + metadata->u.gfx9.dcc_pitch_max = surface->u.gfx9.color.display_dcc_pitch_max; + metadata->u.gfx9.dcc_independent_64b_blocks = surface->u.gfx9.color.dcc.independent_64B_blocks; + metadata->u.gfx9.dcc_independent_128b_blocks = surface->u.gfx9.color.dcc.independent_128B_blocks; metadata->u.gfx9.dcc_max_compressed_block_size = - surface->u.gfx9.dcc.max_compressed_block_size; + surface->u.gfx9.color.dcc.max_compressed_block_size; metadata->u.gfx9.scanout = (surface->flags & RADEON_SURF_SCANOUT) != 0; } else { metadata->u.legacy.microtile = surface->u.legacy.level[0].mode >= RADEON_SURF_MODE_1D @@ -1355,7 +1355,7 @@ radv_image_init_retile_map(struct radv_device *device, struct radv_image *image) return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY); } - memcpy(data, image->planes[0].surface.u.gfx9.dcc_retile_map, retile_map_size); + memcpy(data, image->planes[0].surface.u.gfx9.color.dcc_retile_map, retile_map_size); return VK_SUCCESS; } @@ -1719,7 +1719,7 @@ radv_image_view_make_descriptor(struct radv_image_view *iview, struct radv_devic const struct legacy_surf_level *base_level_info = NULL; if (device->physical_device->rad_info.chip_class <= GFX9) { if (is_stencil) - base_level_info = &plane->surface.u.legacy.stencil_level[iview->base_mip]; + base_level_info = &plane->surface.u.legacy.zs.stencil_level[iview->base_mip]; else base_level_info = &plane->surface.u.legacy.level[iview->base_mip]; } diff --git a/src/amd/vulkan/radv_meta_clear.c b/src/amd/vulkan/radv_meta_clear.c index 2abc1fc40b2..3ac971238a6 100644 --- a/src/amd/vulkan/radv_meta_clear.c +++ b/src/amd/vulkan/radv_meta_clear.c @@ -1290,7 +1290,7 @@ radv_clear_dcc(struct radv_cmd_buffer *cmd_buffer, struct radv_image *image, size = image->planes[0].surface.meta_size; } else { const struct legacy_surf_dcc_level *dcc_level = - &image->planes[0].surface.u.legacy.dcc_level[level]; + &image->planes[0].surface.u.legacy.color.dcc_level[level]; /* If dcc_fast_clear_size is 0 (which might happens for * mipmaps) the fill buffer operation below is a no-op. @@ -1515,7 +1515,7 @@ radv_can_fast_clear_color(struct radv_cmd_buffer *cmd_buffer, const struct radv_ for (uint32_t l = 0; l < iview->level_count; l++) { uint32_t level = iview->base_mip + l; struct legacy_surf_dcc_level *dcc_level = - &iview->image->planes[0].surface.u.legacy.dcc_level[level]; + &iview->image->planes[0].surface.u.legacy.color.dcc_level[level]; /* Do not fast clears if one level can't be * fast cleared. diff --git a/src/amd/vulkan/radv_meta_dcc_retile.c b/src/amd/vulkan/radv_meta_dcc_retile.c index ece65e94081..5240caf0fe4 100644 --- a/src/amd/vulkan/radv_meta_dcc_retile.c +++ b/src/amd/vulkan/radv_meta_dcc_retile.c @@ -227,7 +227,7 @@ radv_retile_dcc(struct radv_cmd_buffer *cmd_buffer, struct radv_image *image) .buffer = radv_buffer_to_handle(&retile_buffer), .offset = 0, .range = retile_map_size, - .format = image->planes[0].surface.u.gfx9.dcc_retile_use_uint16 ? VK_FORMAT_R16G16_UINT + .format = image->planes[0].surface.u.gfx9.color.dcc_retile_use_uint16 ? VK_FORMAT_R16G16_UINT : VK_FORMAT_R32G32_UINT, }); radv_buffer_view_init(views + 1, cmd_buffer->device, @@ -243,7 +243,7 @@ radv_retile_dcc(struct radv_cmd_buffer *cmd_buffer, struct radv_image *image) .sType = VK_STRUCTURE_TYPE_BUFFER_VIEW_CREATE_INFO, .buffer = radv_buffer_to_handle(&buffer), .offset = image->planes[0].surface.display_dcc_offset, - .range = image->planes[0].surface.u.gfx9.display_dcc_size, + .range = image->planes[0].surface.u.gfx9.color.display_dcc_size, .format = VK_FORMAT_R8_UINT, }); for (unsigned i = 0; i < 3; ++i) @@ -281,7 +281,7 @@ radv_retile_dcc(struct radv_cmd_buffer *cmd_buffer, struct radv_image *image) /* src+dst pairs count double, so the number of DCC bytes we move is * actually half of dcc_retile_num_elements. */ - radv_unaligned_dispatch(cmd_buffer, image->planes[0].surface.u.gfx9.dcc_retile_num_elements / 2, + radv_unaligned_dispatch(cmd_buffer, image->planes[0].surface.u.gfx9.color.dcc_retile_num_elements / 2, 1, 1); radv_meta_restore(&saved_state, cmd_buffer); diff --git a/src/gallium/drivers/r600/evergreen_state.c b/src/gallium/drivers/r600/evergreen_state.c index f9340baa6e8..f76b1e331a8 100644 --- a/src/gallium/drivers/r600/evergreen_state.c +++ b/src/gallium/drivers/r600/evergreen_state.c @@ -756,7 +756,7 @@ static int evergreen_fill_tex_resource_words(struct r600_context *rctx, case PIPE_FORMAT_X32_S8X24_UINT: params->pipe_format = PIPE_FORMAT_S8_UINT; tile_split = tmp->surface.u.legacy.stencil_tile_split; - surflevel = tmp->surface.u.legacy.stencil_level; + surflevel = tmp->surface.u.legacy.zs.stencil_level; break; default:; } @@ -1411,7 +1411,7 @@ static void evergreen_init_depth_surface(struct r600_context *rctx, stile_split = eg_tile_split(stile_split); - stencil_offset = (uint64_t)rtex->surface.u.legacy.stencil_level[level].offset_256B * 256; + stencil_offset = (uint64_t)rtex->surface.u.legacy.zs.stencil_level[level].offset_256B * 256; stencil_offset += rtex->resource.gpu_address; surf->db_stencil_base = stencil_offset >> 8; diff --git a/src/gallium/drivers/r600/r600_texture.c b/src/gallium/drivers/r600/r600_texture.c index d24520bb597..c910bd08bfc 100644 --- a/src/gallium/drivers/r600/r600_texture.c +++ b/src/gallium/drivers/r600/r600_texture.c @@ -886,15 +886,15 @@ void r600_print_texture_info(struct r600_common_screen *rscreen, "slice_size=%"PRIu64", npix_x=%u, " "npix_y=%u, npix_z=%u, nblk_x=%u, nblk_y=%u, " "mode=%u, tiling_index = %u\n", - i, (uint64_t)rtex->surface.u.legacy.stencil_level[i].offset_256B * 256, - (uint64_t)rtex->surface.u.legacy.stencil_level[i].slice_size_dw * 4, + i, (uint64_t)rtex->surface.u.legacy.zs.stencil_level[i].offset_256B * 256, + (uint64_t)rtex->surface.u.legacy.zs.stencil_level[i].slice_size_dw * 4, u_minify(rtex->resource.b.b.width0, i), u_minify(rtex->resource.b.b.height0, i), u_minify(rtex->resource.b.b.depth0, i), - rtex->surface.u.legacy.stencil_level[i].nblk_x, - rtex->surface.u.legacy.stencil_level[i].nblk_y, - rtex->surface.u.legacy.stencil_level[i].mode, - rtex->surface.u.legacy.stencil_tiling_index[i]); + rtex->surface.u.legacy.zs.stencil_level[i].nblk_x, + rtex->surface.u.legacy.zs.stencil_level[i].nblk_y, + rtex->surface.u.legacy.zs.stencil_level[i].mode, + rtex->surface.u.legacy.zs.stencil_tiling_index[i]); } } } diff --git a/src/gallium/drivers/radeonsi/si_blit.c b/src/gallium/drivers/radeonsi/si_blit.c index 9cf477f1b00..521ba3cd18e 100644 --- a/src/gallium/drivers/radeonsi/si_blit.c +++ b/src/gallium/drivers/radeonsi/si_blit.c @@ -500,7 +500,7 @@ static void si_blit_decompress_color(struct si_context *sctx, struct si_texture sctx->decompression_enabled = false; si_make_CB_shader_coherent(sctx, tex->buffer.b.b.nr_samples, vi_dcc_enabled(tex, first_level), - tex->surface.u.gfx9.dcc.pipe_aligned); + tex->surface.u.gfx9.color.dcc.pipe_aligned); expand_fmask: if (need_fmask_expand && tex->surface.fmask_offset && !tex->fmask_is_identity) { diff --git a/src/gallium/drivers/radeonsi/si_clear.c b/src/gallium/drivers/radeonsi/si_clear.c index 5cbfa50714c..3d01b18f2ab 100644 --- a/src/gallium/drivers/radeonsi/si_clear.c +++ b/src/gallium/drivers/radeonsi/si_clear.c @@ -294,7 +294,7 @@ bool vi_dcc_get_clear_info(struct si_context *sctx, struct si_texture *tex, unsi unsigned num_layers = util_num_layers(&tex->buffer.b.b, level); /* If this is 0, fast clear isn't possible. (can occur with MSAA) */ - if (!tex->surface.u.legacy.dcc_level[level].dcc_fast_clear_size) + if (!tex->surface.u.legacy.color.dcc_level[level].dcc_fast_clear_size) return false; /* Layered 4x and 8x MSAA DCC fast clears need to clear @@ -304,8 +304,8 @@ bool vi_dcc_get_clear_info(struct si_context *sctx, struct si_texture *tex, unsi if (tex->buffer.b.b.nr_storage_samples >= 4 && num_layers > 1) return false; - dcc_offset += tex->surface.u.legacy.dcc_level[level].dcc_offset; - clear_size = tex->surface.u.legacy.dcc_level[level].dcc_fast_clear_size * num_layers; + dcc_offset += tex->surface.u.legacy.color.dcc_level[level].dcc_offset; + clear_size = tex->surface.u.legacy.color.dcc_level[level].dcc_fast_clear_size * num_layers; } si_init_buffer_clear(out, dcc_buffer, dcc_offset, clear_size, clear_value); diff --git a/src/gallium/drivers/radeonsi/si_compute_blit.c b/src/gallium/drivers/radeonsi/si_compute_blit.c index 008a3756908..10d12ca6de4 100644 --- a/src/gallium/drivers/radeonsi/si_compute_blit.c +++ b/src/gallium/drivers/radeonsi/si_compute_blit.c @@ -466,7 +466,7 @@ void si_compute_copy_image(struct si_context *sctx, struct pipe_resource *dst, u /* src and dst have the same number of samples. */ si_make_CB_shader_coherent(sctx, src->nr_samples, true, /* Only src can have DCC.*/ - ((struct si_texture *)src)->surface.u.gfx9.dcc.pipe_aligned); + ((struct si_texture *)src)->surface.u.gfx9.color.dcc.pipe_aligned); struct si_images *images = &sctx->images[PIPE_SHADER_COMPUTE]; struct pipe_image_view saved_image[2] = {0}; @@ -529,9 +529,9 @@ void si_compute_copy_image(struct si_context *sctx, struct pipe_resource *dst, u sctx->cs_dcc_decompress = si_create_dcc_decompress_cs(ctx); ctx->bind_compute_state(ctx, sctx->cs_dcc_decompress); - info.block[0] = tex->surface.u.gfx9.dcc_block_width; - info.block[1] = tex->surface.u.gfx9.dcc_block_height; - info.block[2] = tex->surface.u.gfx9.dcc_block_depth; + info.block[0] = tex->surface.u.gfx9.color.dcc_block_width; + info.block[1] = tex->surface.u.gfx9.color.dcc_block_height; + info.block[2] = tex->surface.u.gfx9.color.dcc_block_depth; /* Make sure the block size is at least the same as wave size. */ while (info.block[0] * info.block[1] * info.block[2] < @@ -597,8 +597,8 @@ void si_retile_dcc(struct si_context *sctx, struct si_texture *tex) } /* Set images. */ - bool use_uint16 = tex->surface.u.gfx9.dcc_retile_use_uint16; - unsigned num_elements = tex->surface.u.gfx9.dcc_retile_num_elements; + bool use_uint16 = tex->surface.u.gfx9.color.dcc_retile_use_uint16; + unsigned num_elements = tex->surface.u.gfx9.color.dcc_retile_num_elements; struct pipe_image_view img[3]; assert(tex->dcc_retile_buffer); @@ -621,7 +621,7 @@ void si_retile_dcc(struct si_context *sctx, struct si_texture *tex) img[2].format = PIPE_FORMAT_R8_UINT; img[2].u.buf.offset = tex->surface.display_dcc_offset; - img[2].u.buf.size = tex->surface.u.gfx9.display_dcc_size; + img[2].u.buf.size = tex->surface.u.gfx9.color.display_dcc_size; ctx->set_shader_images(ctx, PIPE_SHADER_COMPUTE, 0, 3, 0, img); diff --git a/src/gallium/drivers/radeonsi/si_descriptors.c b/src/gallium/drivers/radeonsi/si_descriptors.c index 416e11c6c31..c3a81daa434 100644 --- a/src/gallium/drivers/radeonsi/si_descriptors.c +++ b/src/gallium/drivers/radeonsi/si_descriptors.c @@ -310,7 +310,7 @@ void si_set_mutable_tex_desc_fields(struct si_screen *sscreen, struct si_texture if (sscreen->info.chip_class >= GFX9) { /* Only stencil_offset needs to be added here. */ if (is_stencil) - va += tex->surface.u.gfx9.stencil_offset; + va += tex->surface.u.gfx9.zs.stencil_offset; else va += tex->surface.u.gfx9.surf_offset; } else { @@ -335,7 +335,7 @@ void si_set_mutable_tex_desc_fields(struct si_screen *sscreen, struct si_texture (!tex->dcc_separate_buffer ? tex->buffer.gpu_address : 0) + tex->surface.meta_offset; if (sscreen->info.chip_class == GFX8) { - meta_va += tex->surface.u.legacy.dcc_level[base_level].dcc_offset; + meta_va += tex->surface.u.legacy.color.dcc_level[base_level].dcc_offset; assert(base_level_info->mode == RADEON_SURF_MODE_2D); } @@ -358,7 +358,7 @@ void si_set_mutable_tex_desc_fields(struct si_screen *sscreen, struct si_texture state[3] &= C_00A00C_SW_MODE; if (is_stencil) { - state[3] |= S_00A00C_SW_MODE(tex->surface.u.gfx9.stencil_swizzle_mode); + state[3] |= S_00A00C_SW_MODE(tex->surface.u.gfx9.zs.stencil_swizzle_mode); } else { state[3] |= S_00A00C_SW_MODE(tex->surface.u.gfx9.swizzle_mode); } @@ -373,7 +373,7 @@ void si_set_mutable_tex_desc_fields(struct si_screen *sscreen, struct si_texture }; if (!tex->is_depth && tex->surface.meta_offset) - meta = tex->surface.u.gfx9.dcc; + meta = tex->surface.u.gfx9.color.dcc; state[6] |= S_00A018_META_PIPE_ALIGNED(meta.pipe_aligned) | S_00A018_META_DATA_ADDRESS_LO(meta_va >> 8) | @@ -386,8 +386,8 @@ void si_set_mutable_tex_desc_fields(struct si_screen *sscreen, struct si_texture state[4] &= C_008F20_PITCH; if (is_stencil) { - state[3] |= S_008F1C_SW_MODE(tex->surface.u.gfx9.stencil_swizzle_mode); - state[4] |= S_008F20_PITCH(tex->surface.u.gfx9.stencil_epitch); + state[3] |= S_008F1C_SW_MODE(tex->surface.u.gfx9.zs.stencil_swizzle_mode); + state[4] |= S_008F20_PITCH(tex->surface.u.gfx9.zs.stencil_epitch); } else { uint16_t epitch = tex->surface.u.gfx9.epitch; if (tex->buffer.b.b.format == PIPE_FORMAT_R8G8_R8B8_UNORM && @@ -412,7 +412,7 @@ void si_set_mutable_tex_desc_fields(struct si_screen *sscreen, struct si_texture }; if (!tex->is_depth && tex->surface.meta_offset) - meta = tex->surface.u.gfx9.dcc; + meta = tex->surface.u.gfx9.color.dcc; state[5] |= S_008F24_META_DATA_ADDRESS(meta_va >> 40) | S_008F24_META_PIPE_ALIGNED(meta.pipe_aligned) | diff --git a/src/gallium/drivers/radeonsi/si_pipe.h b/src/gallium/drivers/radeonsi/si_pipe.h index cd35cf5010c..70dbf8444d7 100644 --- a/src/gallium/drivers/radeonsi/si_pipe.h +++ b/src/gallium/drivers/radeonsi/si_pipe.h @@ -1663,7 +1663,7 @@ static inline bool vi_dcc_enabled(struct si_texture *tex, unsigned level) static inline unsigned si_tile_mode_index(struct si_texture *tex, unsigned level, bool stencil) { if (stencil) - return tex->surface.u.legacy.stencil_tiling_index[level]; + return tex->surface.u.legacy.zs.stencil_tiling_index[level]; else return tex->surface.u.legacy.tiling_index[level]; } diff --git a/src/gallium/drivers/radeonsi/si_state.c b/src/gallium/drivers/radeonsi/si_state.c index 5f43a1409eb..22dbd725046 100644 --- a/src/gallium/drivers/radeonsi/si_state.c +++ b/src/gallium/drivers/radeonsi/si_state.c @@ -2359,7 +2359,7 @@ static void si_initialize_color_surface(struct si_context *sctx, struct si_surfa if (tex->surface.fmask_offset) { color_info |= S_028C70_COMPRESSION(1); - unsigned fmask_bankh = util_logbase2(tex->surface.u.legacy.fmask.bankh); + unsigned fmask_bankh = util_logbase2(tex->surface.u.legacy.color.fmask.bankh); if (sctx->chip_class == GFX6) { /* due to a hw bug, FMASK_BANK_HEIGHT must be set on GFX6 too */ @@ -2378,10 +2378,10 @@ static void si_initialize_color_surface(struct si_context *sctx, struct si_surfa if (sctx->chip_class >= GFX10) { surf->cb_dcc_control = S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(V_028C78_MAX_BLOCK_SIZE_256B) | - S_028C78_MAX_COMPRESSED_BLOCK_SIZE(tex->surface.u.gfx9.dcc.max_compressed_block_size) | + S_028C78_MAX_COMPRESSED_BLOCK_SIZE(tex->surface.u.gfx9.color.dcc.max_compressed_block_size) | S_028C78_MIN_COMPRESSED_BLOCK_SIZE(min_compressed_block_size) | - S_028C78_INDEPENDENT_64B_BLOCKS(tex->surface.u.gfx9.dcc.independent_64B_blocks) | - S_028C78_INDEPENDENT_128B_BLOCKS(tex->surface.u.gfx9.dcc.independent_128B_blocks); + S_028C78_INDEPENDENT_64B_BLOCKS(tex->surface.u.gfx9.color.dcc.independent_64B_blocks) | + S_028C78_INDEPENDENT_128B_BLOCKS(tex->surface.u.gfx9.color.dcc.independent_128B_blocks); } else if (sctx->chip_class >= GFX8) { unsigned max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_256B; @@ -2463,17 +2463,17 @@ static void si_init_depth_surface(struct si_context *sctx, struct si_surface *su if (sctx->chip_class >= GFX9) { assert(tex->surface.u.gfx9.surf_offset == 0); surf->db_depth_base = tex->buffer.gpu_address >> 8; - surf->db_stencil_base = (tex->buffer.gpu_address + tex->surface.u.gfx9.stencil_offset) >> 8; + surf->db_stencil_base = (tex->buffer.gpu_address + tex->surface.u.gfx9.zs.stencil_offset) >> 8; z_info = S_028038_FORMAT(format) | S_028038_NUM_SAMPLES(util_logbase2(tex->buffer.b.b.nr_samples)) | S_028038_SW_MODE(tex->surface.u.gfx9.swizzle_mode) | S_028038_MAXMIP(tex->buffer.b.b.last_level); s_info = S_02803C_FORMAT(stencil_format) | - S_02803C_SW_MODE(tex->surface.u.gfx9.stencil_swizzle_mode); + S_02803C_SW_MODE(tex->surface.u.gfx9.zs.stencil_swizzle_mode); if (sctx->chip_class == GFX9) { surf->db_z_info2 = S_028068_EPITCH(tex->surface.u.gfx9.epitch); - surf->db_stencil_info2 = S_02806C_EPITCH(tex->surface.u.gfx9.stencil_epitch); + surf->db_stencil_info2 = S_02806C_EPITCH(tex->surface.u.gfx9.zs.stencil_epitch); } surf->db_depth_view |= S_028008_MIPID(level); surf->db_depth_size = @@ -2508,7 +2508,7 @@ static void si_init_depth_surface(struct si_context *sctx, struct si_surface *su surf->db_depth_base = (tex->buffer.gpu_address >> 8) + tex->surface.u.legacy.level[level].offset_256B; surf->db_stencil_base = - (tex->buffer.gpu_address >> 8) + tex->surface.u.legacy.stencil_level[level].offset_256B; + (tex->buffer.gpu_address >> 8) + tex->surface.u.legacy.zs.stencil_level[level].offset_256B; z_info = S_028040_FORMAT(format) | S_028040_NUM_SAMPLES(util_logbase2(tex->buffer.b.b.nr_samples)); @@ -2518,7 +2518,7 @@ static void si_init_depth_surface(struct si_context *sctx, struct si_surface *su if (sctx->chip_class >= GFX7) { struct radeon_info *info = &sctx->screen->info; unsigned index = tex->surface.u.legacy.tiling_index[level]; - unsigned stencil_index = tex->surface.u.legacy.stencil_tiling_index[level]; + unsigned stencil_index = tex->surface.u.legacy.zs.stencil_tiling_index[level]; unsigned macro_index = tex->surface.u.legacy.macro_tile_index; unsigned tile_mode = info->si_tile_mode_array[index]; unsigned stencil_tile_mode = info->si_tile_mode_array[stencil_index]; @@ -2829,7 +2829,7 @@ static void si_set_framebuffer_state(struct pipe_context *ctx, if (vi_dcc_enabled(tex, surf->base.u.tex.level)) { sctx->framebuffer.CB_has_shader_readable_metadata = true; - if (sctx->chip_class >= GFX9 && !tex->surface.u.gfx9.dcc.pipe_aligned) + if (sctx->chip_class >= GFX9 && !tex->surface.u.gfx9.color.dcc.pipe_aligned) sctx->framebuffer.all_DCC_pipe_aligned = false; if (tex->buffer.b.b.nr_storage_samples >= 2) @@ -3052,9 +3052,9 @@ static void si_emit_framebuffer_state(struct si_context *sctx) cb_color_attrib3 = cb->cb_color_attrib3 | S_028EE0_COLOR_SW_MODE(tex->surface.u.gfx9.swizzle_mode) | - S_028EE0_FMASK_SW_MODE(tex->surface.u.gfx9.fmask_swizzle_mode) | + S_028EE0_FMASK_SW_MODE(tex->surface.u.gfx9.color.fmask_swizzle_mode) | S_028EE0_CMASK_PIPE_ALIGNED(1) | - S_028EE0_DCC_PIPE_ALIGNED(tex->surface.u.gfx9.dcc.pipe_aligned); + S_028EE0_DCC_PIPE_ALIGNED(tex->surface.u.gfx9.color.dcc.pipe_aligned); radeon_set_context_reg_seq(cs, R_028C60_CB_COLOR0_BASE + i * 0x3C, 14); radeon_emit(cs, cb_color_base); /* CB_COLOR0_BASE */ @@ -3087,7 +3087,7 @@ static void si_emit_framebuffer_state(struct si_context *sctx) }; if (!tex->is_depth && tex->surface.meta_offset) - meta = tex->surface.u.gfx9.dcc; + meta = tex->surface.u.gfx9.color.dcc; /* Set mutable surface parameters. */ cb_color_base += tex->surface.u.gfx9.surf_offset >> 8; @@ -3097,7 +3097,7 @@ static void si_emit_framebuffer_state(struct si_context *sctx) if (cb->base.u.tex.level > 0) cb_color_cmask = cb_color_base; cb_color_attrib |= S_028C74_COLOR_SW_MODE(tex->surface.u.gfx9.swizzle_mode) | - S_028C74_FMASK_SW_MODE(tex->surface.u.gfx9.fmask_swizzle_mode) | + S_028C74_FMASK_SW_MODE(tex->surface.u.gfx9.color.fmask_swizzle_mode) | S_028C74_RB_ALIGNED(meta.rb_aligned) | S_028C74_PIPE_ALIGNED(meta.pipe_aligned); @@ -3137,7 +3137,7 @@ static void si_emit_framebuffer_state(struct si_context *sctx) if (cb->base.u.tex.level > 0) cb_color_cmask = cb_color_base; if (cb_dcc_base) - cb_dcc_base += tex->surface.u.legacy.dcc_level[cb->base.u.tex.level].dcc_offset >> 8; + cb_dcc_base += tex->surface.u.legacy.color.dcc_level[cb->base.u.tex.level].dcc_offset >> 8; pitch_tile_max = level_info->nblk_x / 8 - 1; slice_tile_max = level_info->nblk_x * level_info->nblk_y / 64 - 1; @@ -3150,10 +3150,10 @@ static void si_emit_framebuffer_state(struct si_context *sctx) if (tex->surface.fmask_offset) { if (sctx->chip_class >= GFX7) cb_color_pitch |= - S_028C64_FMASK_TILE_MAX(tex->surface.u.legacy.fmask.pitch_in_pixels / 8 - 1); + S_028C64_FMASK_TILE_MAX(tex->surface.u.legacy.color.fmask.pitch_in_pixels / 8 - 1); cb_color_attrib |= - S_028C74_FMASK_TILE_MODE_INDEX(tex->surface.u.legacy.fmask.tiling_index); - cb_color_fmask_slice = S_028C88_TILE_MAX(tex->surface.u.legacy.fmask.slice_tile_max); + S_028C74_FMASK_TILE_MODE_INDEX(tex->surface.u.legacy.color.fmask.tiling_index); + cb_color_fmask_slice = S_028C88_TILE_MAX(tex->surface.u.legacy.color.fmask.slice_tile_max); } else { /* This must be set for fast clear to work without FMASK. */ if (sctx->chip_class >= GFX7) @@ -3172,7 +3172,7 @@ static void si_emit_framebuffer_state(struct si_context *sctx) radeon_emit(cs, cb_color_attrib); /* CB_COLOR0_ATTRIB */ radeon_emit(cs, cb->cb_dcc_control); /* CB_COLOR0_DCC_CONTROL */ radeon_emit(cs, cb_color_cmask); /* CB_COLOR0_CMASK */ - radeon_emit(cs, tex->surface.u.legacy.cmask_slice_tile_max); /* CB_COLOR0_CMASK_SLICE */ + radeon_emit(cs, tex->surface.u.legacy.color.cmask_slice_tile_max); /* CB_COLOR0_CMASK_SLICE */ radeon_emit(cs, cb_color_fmask); /* CB_COLOR0_FMASK */ radeon_emit(cs, cb_color_fmask_slice); /* CB_COLOR0_FMASK_SLICE */ radeon_emit(cs, tex->color_clear_value[0]); /* CB_COLOR0_CLEAR_WORD0 */ @@ -3828,7 +3828,7 @@ static void gfx10_make_texture_descriptor( if (vi_dcc_enabled(tex, first_level)) { state[6] |= S_00A018_MAX_UNCOMPRESSED_BLOCK_SIZE(V_028C78_MAX_BLOCK_SIZE_256B) | - S_00A018_MAX_COMPRESSED_BLOCK_SIZE(tex->surface.u.gfx9.dcc.max_compressed_block_size) | + S_00A018_MAX_COMPRESSED_BLOCK_SIZE(tex->surface.u.gfx9.color.dcc.max_compressed_block_size) | S_00A018_ALPHA_IS_ON_MSB(vi_alpha_is_on_msb(screen, pipe_format)); } @@ -3891,7 +3891,7 @@ static void gfx10_make_texture_descriptor( fmask_state[3] = S_00A00C_DST_SEL_X(V_008F1C_SQ_SEL_X) | S_00A00C_DST_SEL_Y(V_008F1C_SQ_SEL_X) | S_00A00C_DST_SEL_Z(V_008F1C_SQ_SEL_X) | S_00A00C_DST_SEL_W(V_008F1C_SQ_SEL_X) | - S_00A00C_SW_MODE(tex->surface.u.gfx9.fmask_swizzle_mode) | + S_00A00C_SW_MODE(tex->surface.u.gfx9.color.fmask_swizzle_mode) | S_00A00C_TYPE(si_tex_dim(screen, tex, target, 0)); fmask_state[4] = S_00A010_DEPTH(last_layer) | S_00A010_BASE_ARRAY(first_layer); fmask_state[5] = 0; @@ -4215,15 +4215,15 @@ static void si_make_texture_descriptor(struct si_screen *screen, struct si_textu fmask_state[7] = 0; if (screen->info.chip_class == GFX9) { - fmask_state[3] |= S_008F1C_SW_MODE(tex->surface.u.gfx9.fmask_swizzle_mode); + fmask_state[3] |= S_008F1C_SW_MODE(tex->surface.u.gfx9.color.fmask_swizzle_mode); fmask_state[4] |= - S_008F20_DEPTH(last_layer) | S_008F20_PITCH(tex->surface.u.gfx9.fmask_epitch); + S_008F20_DEPTH(last_layer) | S_008F20_PITCH(tex->surface.u.gfx9.color.fmask_epitch); fmask_state[5] |= S_008F24_META_PIPE_ALIGNED(1) | S_008F24_META_RB_ALIGNED(1); } else { - fmask_state[3] |= S_008F1C_TILING_INDEX(tex->surface.u.legacy.fmask.tiling_index); + fmask_state[3] |= S_008F1C_TILING_INDEX(tex->surface.u.legacy.color.fmask.tiling_index); fmask_state[4] |= S_008F20_DEPTH(depth - 1) | - S_008F20_PITCH(tex->surface.u.legacy.fmask.pitch_in_pixels - 1); + S_008F20_PITCH(tex->surface.u.legacy.color.fmask.pitch_in_pixels - 1); fmask_state[5] |= S_008F24_LAST_ARRAY(last_layer); } } @@ -4348,7 +4348,7 @@ struct pipe_sampler_view *si_create_sampler_view_custom(struct pipe_context *ctx case PIPE_FORMAT_S8X24_UINT: case PIPE_FORMAT_X32_S8X24_UINT: pipe_format = PIPE_FORMAT_S8_UINT; - surflevel = tex->surface.u.legacy.stencil_level; + surflevel = tex->surface.u.legacy.zs.stencil_level; break; default:; } diff --git a/src/gallium/drivers/radeonsi/si_texture.c b/src/gallium/drivers/radeonsi/si_texture.c index 511253e86ed..78c03fd2832 100644 --- a/src/gallium/drivers/radeonsi/si_texture.c +++ b/src/gallium/drivers/radeonsi/si_texture.c @@ -836,8 +836,8 @@ void si_print_texture_info(struct si_screen *sscreen, struct si_texture *tex, u_log_printf(log, " DCCLevel[%i]: enabled=%u, offset=%u, " "fast_clear_size=%u\n", - i, i < tex->surface.num_meta_levels, tex->surface.u.legacy.dcc_level[i].dcc_offset, - tex->surface.u.legacy.dcc_level[i].dcc_fast_clear_size); + i, i < tex->surface.num_meta_levels, tex->surface.u.legacy.color.dcc_level[i].dcc_offset, + tex->surface.u.legacy.color.dcc_level[i].dcc_fast_clear_size); } for (i = 0; i <= tex->buffer.b.b.last_level; i++) @@ -859,14 +859,14 @@ void si_print_texture_info(struct si_screen *sscreen, struct si_texture *tex, "slice_size=%" PRIu64 ", npix_x=%u, " "npix_y=%u, npix_z=%u, nblk_x=%u, nblk_y=%u, " "mode=%u, tiling_index = %u\n", - i, (uint64_t)tex->surface.u.legacy.stencil_level[i].offset_256B * 256, - (uint64_t)tex->surface.u.legacy.stencil_level[i].slice_size_dw * 4, + i, (uint64_t)tex->surface.u.legacy.zs.stencil_level[i].offset_256B * 256, + (uint64_t)tex->surface.u.legacy.zs.stencil_level[i].slice_size_dw * 4, u_minify(tex->buffer.b.b.width0, i), u_minify(tex->buffer.b.b.height0, i), u_minify(tex->buffer.b.b.depth0, i), - tex->surface.u.legacy.stencil_level[i].nblk_x, - tex->surface.u.legacy.stencil_level[i].nblk_y, - tex->surface.u.legacy.stencil_level[i].mode, - tex->surface.u.legacy.stencil_tiling_index[i]); + tex->surface.u.legacy.zs.stencil_level[i].nblk_x, + tex->surface.u.legacy.zs.stencil_level[i].nblk_y, + tex->surface.u.legacy.zs.stencil_level[i].mode, + tex->surface.u.legacy.zs.stencil_tiling_index[i]); } } } @@ -1070,11 +1070,11 @@ static struct si_texture *si_texture_create_object(struct pipe_screen *screen, unsigned size = 0; for (unsigned i = 0; i < tex->surface.num_meta_levels; i++) { - if (!tex->surface.u.legacy.dcc_level[i].dcc_fast_clear_size) + if (!tex->surface.u.legacy.color.dcc_level[i].dcc_fast_clear_size) break; - size = tex->surface.u.legacy.dcc_level[i].dcc_offset + - tex->surface.u.legacy.dcc_level[i].dcc_fast_clear_size; + size = tex->surface.u.legacy.color.dcc_level[i].dcc_offset + + tex->surface.u.legacy.color.dcc_level[i].dcc_fast_clear_size; } /* Mipmap levels with DCC. */ @@ -1100,7 +1100,7 @@ static struct si_texture *si_texture_create_object(struct pipe_screen *screen, * Clear to white to indicate that. */ assert(num_clears < ARRAY_SIZE(clears)); si_init_buffer_clear(&clears[num_clears++], &tex->buffer.b.b, tex->surface.display_dcc_offset, - tex->surface.u.gfx9.display_dcc_size, DCC_CLEAR_COLOR_1111); + tex->surface.u.gfx9.color.display_dcc_size, DCC_CLEAR_COLOR_1111); } /* Upload the DCC retile map. @@ -1120,7 +1120,7 @@ static struct si_texture *si_texture_create_object(struct pipe_screen *screen, void *map = sscreen->ws->buffer_map(sscreen->ws, buf->buf, NULL, PIPE_MAP_WRITE); /* Upload the retile map into the staging buffer. */ - memcpy(map, tex->surface.u.gfx9.dcc_retile_map, dcc_retile_map_size); + memcpy(map, tex->surface.u.gfx9.color.dcc_retile_map, dcc_retile_map_size); /* Copy the staging buffer to the buffer backing the texture. */ struct si_context *sctx = (struct si_context *)sscreen->aux_context; diff --git a/src/gallium/winsys/radeon/drm/radeon_drm_surface.c b/src/gallium/winsys/radeon/drm/radeon_drm_surface.c index 405e414a02f..694086b060a 100644 --- a/src/gallium/winsys/radeon/drm/radeon_drm_surface.c +++ b/src/gallium/winsys/radeon/drm/radeon_drm_surface.c @@ -165,9 +165,9 @@ static void surf_winsys_to_drm(struct radeon_surface *surf_drm, for (i = 0; i <= surf_drm->last_level; i++) { surf_level_winsys_to_drm(&surf_drm->stencil_level[i], - &surf_ws->u.legacy.stencil_level[i], + &surf_ws->u.legacy.zs.stencil_level[i], surf_drm->nsamples); - surf_drm->stencil_tiling_index[i] = surf_ws->u.legacy.stencil_tiling_index[i]; + surf_drm->stencil_tiling_index[i] = surf_ws->u.legacy.zs.stencil_tiling_index[i]; } } } @@ -207,10 +207,10 @@ static void surf_drm_to_winsys(struct radeon_drm_winsys *ws, surf_ws->u.legacy.stencil_tile_split = surf_drm->stencil_tile_split; for (i = 0; i <= surf_drm->last_level; i++) { - surf_level_drm_to_winsys(&surf_ws->u.legacy.stencil_level[i], + surf_level_drm_to_winsys(&surf_ws->u.legacy.zs.stencil_level[i], &surf_drm->stencil_level[i], surf_drm->nsamples); - surf_ws->u.legacy.stencil_tiling_index[i] = surf_drm->stencil_tiling_index[i]; + surf_ws->u.legacy.zs.stencil_tiling_index[i] = surf_drm->stencil_tiling_index[i]; } } @@ -264,9 +264,9 @@ static void si_compute_cmask(const struct radeon_info *info, /* Each element of CMASK is a nibble. */ unsigned slice_bytes = slice_elements / 2; - surf->u.legacy.cmask_slice_tile_max = (width * height) / (128*128); - if (surf->u.legacy.cmask_slice_tile_max) - surf->u.legacy.cmask_slice_tile_max -= 1; + surf->u.legacy.color.cmask_slice_tile_max = (width * height) / (128*128); + if (surf->u.legacy.color.cmask_slice_tile_max) + surf->u.legacy.color.cmask_slice_tile_max -= 1; unsigned num_layers; if (config->is_3d) @@ -407,14 +407,14 @@ static int radeon_winsys_surface_init(struct radeon_winsys *rws, surf_ws->fmask_alignment_log2 = util_logbase2(MAX2(256, 1 << fmask.surf_alignment_log2)); surf_ws->fmask_tile_swizzle = fmask.tile_swizzle; - surf_ws->u.legacy.fmask.slice_tile_max = + surf_ws->u.legacy.color.fmask.slice_tile_max = (fmask.u.legacy.level[0].nblk_x * fmask.u.legacy.level[0].nblk_y) / 64; - if (surf_ws->u.legacy.fmask.slice_tile_max) - surf_ws->u.legacy.fmask.slice_tile_max -= 1; + if (surf_ws->u.legacy.color.fmask.slice_tile_max) + surf_ws->u.legacy.color.fmask.slice_tile_max -= 1; - surf_ws->u.legacy.fmask.tiling_index = fmask.u.legacy.tiling_index[0]; - surf_ws->u.legacy.fmask.bankh = fmask.u.legacy.bankh; - surf_ws->u.legacy.fmask.pitch_in_pixels = fmask.u.legacy.level[0].nblk_x; + surf_ws->u.legacy.color.fmask.tiling_index = fmask.u.legacy.tiling_index[0]; + surf_ws->u.legacy.color.fmask.bankh = fmask.u.legacy.bankh; + surf_ws->u.legacy.color.fmask.pitch_in_pixels = fmask.u.legacy.level[0].nblk_x; } if (ws->gen == DRV_SI &&