diff --git a/src/gallium/drivers/radeonsi/si_state.c b/src/gallium/drivers/radeonsi/si_state.c
index 22dbd725046..ce49d66a54c 100644
--- a/src/gallium/drivers/radeonsi/si_state.c
+++ b/src/gallium/drivers/radeonsi/si_state.c
@@ -5428,7 +5428,7 @@ void si_init_cs_preamble_state(struct si_context *sctx, bool uses_reg_shadowing)
                      S_00B0C0_NUMBER_OF_REQUESTS_PER_CU(4 - 1));
       si_pm4_set_reg(pm4, R_00B1C0_SPI_SHADER_REQ_CTRL_VS, 0);
 
-      /* Enable CMASK/FMASK/HTILE/DCC caching in L2 for small chips. */
+      /* Enable CMASK/HTILE/DCC caching in L2 for small chips. */
       unsigned meta_write_policy, meta_read_policy;
       if (sscreen->info.max_render_backends <= 4) {
          meta_write_policy = V_02807C_CACHE_LRU_WR; /* cache writes */
@@ -5448,11 +5448,12 @@ void si_init_cs_preamble_state(struct si_context *sctx, bool uses_reg_shadowing)
                      S_02807C_HTILE_RD_POLICY(meta_read_policy));
       si_pm4_set_reg(pm4, R_028410_CB_RMI_GL2_CACHE_CONTROL,
                      S_028410_CMASK_WR_POLICY(meta_write_policy) |
-                     S_028410_FMASK_WR_POLICY(meta_write_policy) |
+                     S_028410_FMASK_WR_POLICY(V_028410_CACHE_STREAM) |
                      S_028410_DCC_WR_POLICY(meta_write_policy) |
                      S_028410_COLOR_WR_POLICY(V_028410_CACHE_STREAM) |
                      S_028410_CMASK_RD_POLICY(meta_read_policy) |
-                     S_028410_FMASK_RD_POLICY(meta_read_policy) | S_028410_DCC_RD_POLICY(meta_read_policy) |
+                     S_028410_FMASK_RD_POLICY(V_028410_CACHE_NOA) |
+                     S_028410_DCC_RD_POLICY(meta_read_policy) |
                      S_028410_COLOR_RD_POLICY(V_028410_CACHE_NOA));
 
       si_pm4_set_reg(pm4, R_028428_CB_COVERAGE_OUT_CONTROL, 0);