From fa1129540a5bb472f4681bd49bb36b5d2338e3e2 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Roberto=20de=20Souza?= Date: Thu, 27 Jun 2024 13:17:24 -0700 Subject: [PATCH] intel/dev: Add documentation about intel_device_info_pat_entry::mmap MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit My initial understating was that L3_CACHE_POLICY would be the CPU caching mode but that has nothing to do with CPU caching, it is the GPU caching mode. Due this miss understating we were using a not optimal PAT index that will be fixed in the next patches, so to avoid such issues in future adding comments to intel_device_info_pat_entry struct. Reviewed-by: Jordan Justen Reviewed-by: Jianxun Zhang Signed-off-by: José Roberto de Souza Part-of: --- src/intel/dev/intel_device_info.py | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/src/intel/dev/intel_device_info.py b/src/intel/dev/intel_device_info.py index 6f6aab2f88d..e09bf454f2a 100644 --- a/src/intel/dev/intel_device_info.py +++ b/src/intel/dev/intel_device_info.py @@ -156,7 +156,10 @@ Enum("intel_device_info_coherency_mode", Struct("intel_device_info_pat_entry", [Member("uint8_t", "index"), - Member("intel_device_info_mmap_mode", "mmap"), + Member("intel_device_info_mmap_mode", "mmap", + comment=dedent("""\ + This tells KMD what caching mode the CPU mapping should use. + It has nothing to do with any PAT cache modes.""")), Member("intel_device_info_coherency_mode", "coherency")]) Enum("intel_cmat_scope",