From f9eb0c13a03bc4250887b6e9c3daf66e198bf714 Mon Sep 17 00:00:00 2001 From: Rob Clark Date: Sun, 16 Oct 2022 13:01:38 -0700 Subject: [PATCH] freedreno/a6xx: Drop max_scissor tracking We don't actually really use this on a6xx, since SQE can early-exit IB2 when there are no more remaining primitives in the bin. Signed-off-by: Rob Clark Part-of: --- src/gallium/drivers/freedreno/a6xx/fd6_emit.c | 9 --------- src/gallium/drivers/freedreno/a6xx/fd6_gmem.c | 12 +++++++----- 2 files changed, 7 insertions(+), 14 deletions(-) diff --git a/src/gallium/drivers/freedreno/a6xx/fd6_emit.c b/src/gallium/drivers/freedreno/a6xx/fd6_emit.c index 20ac0788184..858f79a7c81 100644 --- a/src/gallium/drivers/freedreno/a6xx/fd6_emit.c +++ b/src/gallium/drivers/freedreno/a6xx/fd6_emit.c @@ -742,15 +742,6 @@ build_scissor(struct fd6_emit *emit) assert_dt A6XX_GRAS_SC_SCREEN_SCISSOR_BR(0, .x = MAX2(scissor->maxx, 1) - 1, .y = MAX2(scissor->maxy, 1) - 1)); - ctx->batch->max_scissor.minx = - MIN2(ctx->batch->max_scissor.minx, scissor->minx); - ctx->batch->max_scissor.miny = - MIN2(ctx->batch->max_scissor.miny, scissor->miny); - ctx->batch->max_scissor.maxx = - MAX2(ctx->batch->max_scissor.maxx, scissor->maxx); - ctx->batch->max_scissor.maxy = - MAX2(ctx->batch->max_scissor.maxy, scissor->maxy); - return ring; } diff --git a/src/gallium/drivers/freedreno/a6xx/fd6_gmem.c b/src/gallium/drivers/freedreno/a6xx/fd6_gmem.c index f7dead74a50..33ddaeab71d 100644 --- a/src/gallium/drivers/freedreno/a6xx/fd6_gmem.c +++ b/src/gallium/drivers/freedreno/a6xx/fd6_gmem.c @@ -966,12 +966,14 @@ fd6_emit_tile_prep(struct fd_batch *batch, const struct fd_tile *tile) static void set_blit_scissor(struct fd_batch *batch, struct fd_ringbuffer *ring) { - struct pipe_scissor_state blit_scissor = batch->max_scissor; + const struct pipe_framebuffer_state *pfb = &batch->framebuffer; - blit_scissor.minx = ROUND_DOWN_TO(blit_scissor.minx, 16); - blit_scissor.miny = ROUND_DOWN_TO(blit_scissor.miny, 4); - blit_scissor.maxx = ALIGN(blit_scissor.maxx, 16); - blit_scissor.maxy = ALIGN(blit_scissor.maxy, 4); + struct pipe_scissor_state blit_scissor; + + blit_scissor.minx = 0; + blit_scissor.miny = 0; + blit_scissor.maxx = ALIGN(pfb->width, 16); + blit_scissor.maxy = ALIGN(pfb->height, 4); OUT_PKT4(ring, REG_A6XX_RB_BLIT_SCISSOR_TL, 2); OUT_RING(ring, A6XX_RB_BLIT_SCISSOR_TL_X(blit_scissor.minx) |