From f9e76e8ca67d2f1d16d0df6d8576eed2c075f96f Mon Sep 17 00:00:00 2001 From: Lionel Landwerlin Date: Wed, 30 Oct 2024 09:48:37 +0000 Subject: [PATCH] anv: add texture cache inval after binding pool update MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Cc: mesa-stable Reviewed-by: José Roberto de Souza Part-of: --- src/intel/vulkan/genX_cmd_buffer.c | 14 +++++++++++++- 1 file changed, 13 insertions(+), 1 deletion(-) diff --git a/src/intel/vulkan/genX_cmd_buffer.c b/src/intel/vulkan/genX_cmd_buffer.c index 535b11b08af..d338a100c70 100644 --- a/src/intel/vulkan/genX_cmd_buffer.c +++ b/src/intel/vulkan/genX_cmd_buffer.c @@ -381,6 +381,17 @@ genX(cmd_buffer_emit_bt_pool_base_address)(struct anv_cmd_buffer *cmd_buffer) struct anv_device *device = cmd_buffer->device; const uint32_t mocs = isl_mocs(&device->isl_dev, 0, false); + /* We're changing base location of binding tables which affects the state + * cache. We're adding texture cache invalidation following a + * recommendation from the ICL PRMs, Volume 9: Render Engine, Coherency + * Mechanisms: + * + * "It is strongly recommended that a Texture cache invalidation be done + * whenever a State cache invalidation is done." + * + * Prior to do the invalidation, we need a CS_STALL to ensure that all work + * using surface states has completed. + */ genx_batch_emit_pipe_control(&cmd_buffer->batch, cmd_buffer->device->info, cmd_buffer->state.current_pipeline, @@ -392,11 +403,12 @@ genX(cmd_buffer_emit_bt_pool_base_address)(struct anv_cmd_buffer *cmd_buffer) btpa.BindingTablePoolBufferSize = device->physical->va.binding_table_pool.size / 4096; btpa.MOCS = mocs; } - genx_batch_emit_pipe_control(&cmd_buffer->batch, cmd_buffer->device->info, cmd_buffer->state.current_pipeline, + ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT | ANV_PIPE_STATE_CACHE_INVALIDATE_BIT); + #else /* GFX_VERx10 < 125 */ genX(cmd_buffer_emit_state_base_address)(cmd_buffer); #endif