From f9d54b1d36bcb536f3f5efbd2135a4459698e93b Mon Sep 17 00:00:00 2001 From: Qiang Yu Date: Sat, 15 Apr 2023 14:35:27 +0800 Subject: [PATCH] ac/llvm,radeonsi: lower idiv in nir MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit aco does not implement these idiv ops. nir_lower_idiv is for idiv ops <= 32bit and ported from llvm amdgpu, so llvm do the same. nir_lower_divmod64 is for 64bit idiv ops. Reviewed-by: Marek Olšák Signed-off-by: Qiang Yu Part-of: --- src/amd/llvm/ac_nir_to_llvm.c | 15 --------------- src/gallium/drivers/radeonsi/si_get.c | 1 + src/gallium/drivers/radeonsi/si_shader.c | 6 ++++++ 3 files changed, 7 insertions(+), 15 deletions(-) diff --git a/src/amd/llvm/ac_nir_to_llvm.c b/src/amd/llvm/ac_nir_to_llvm.c index 97373ee5c62..fa505250f2d 100644 --- a/src/amd/llvm/ac_nir_to_llvm.c +++ b/src/amd/llvm/ac_nir_to_llvm.c @@ -673,21 +673,6 @@ static bool visit_alu(struct ac_nir_context *ctx, const nir_alu_instr *instr) else result = LLVMBuildMul(ctx->ac.builder, src[0], src[1], ""); break; - case nir_op_imod: - result = LLVMBuildSRem(ctx->ac.builder, src[0], src[1], ""); - break; - case nir_op_umod: - result = LLVMBuildURem(ctx->ac.builder, src[0], src[1], ""); - break; - case nir_op_irem: - result = LLVMBuildSRem(ctx->ac.builder, src[0], src[1], ""); - break; - case nir_op_idiv: - result = LLVMBuildSDiv(ctx->ac.builder, src[0], src[1], ""); - break; - case nir_op_udiv: - result = LLVMBuildUDiv(ctx->ac.builder, src[0], src[1], ""); - break; case nir_op_fmul: src[0] = ac_to_float(&ctx->ac, src[0]); src[1] = ac_to_float(&ctx->ac, src[1]); diff --git a/src/gallium/drivers/radeonsi/si_get.c b/src/gallium/drivers/radeonsi/si_get.c index c1d09620a87..46853b2f6ff 100644 --- a/src/gallium/drivers/radeonsi/si_get.c +++ b/src/gallium/drivers/radeonsi/si_get.c @@ -1328,6 +1328,7 @@ void si_init_screen_get_functions(struct si_screen *sscreen) .support_indirect_inputs = BITFIELD_BIT(MESA_SHADER_TESS_CTRL) | BITFIELD_BIT(MESA_SHADER_TESS_EVAL), .support_indirect_outputs = BITFIELD_BIT(MESA_SHADER_TESS_CTRL), + .lower_int64_options = nir_lower_divmod64, }; sscreen->nir_options = nir_options; } diff --git a/src/gallium/drivers/radeonsi/si_shader.c b/src/gallium/drivers/radeonsi/si_shader.c index 13a463c6e15..c73064652b3 100644 --- a/src/gallium/drivers/radeonsi/si_shader.c +++ b/src/gallium/drivers/radeonsi/si_shader.c @@ -2243,6 +2243,12 @@ struct nir_shader *si_get_nir_shader(struct si_shader *shader, progress2 = true; } + NIR_PASS(progress2, nir, nir_opt_idiv_const, 8); + NIR_PASS(progress2, nir, nir_lower_idiv, + &(nir_lower_idiv_options){ + .allow_fp16 = sel->screen->info.gfx_level >= GFX9, + }); + NIR_PASS(progress2, nir, si_nir_lower_abi, shader, args); if (progress2 || opt_offsets)