diff --git a/src/amd/compiler/aco_ir.cpp b/src/amd/compiler/aco_ir.cpp index da5648e40e8..2f2b5d20289 100644 --- a/src/amd/compiler/aco_ir.cpp +++ b/src/amd/compiler/aco_ir.cpp @@ -833,19 +833,17 @@ get_reduction_identity(ReduceOp op, unsigned idx) return 0; } -unsigned -get_operand_size(aco_ptr& instr, unsigned index) +aco_type +get_operand_type(aco_ptr& alu, unsigned index) { - if (instr->isPseudo()) - return instr->operands[index].bytes() * 8u; - else if (instr->opcode == aco_opcode::v_fma_mix_f32 || - instr->opcode == aco_opcode::v_fma_mixlo_f16 || - instr->opcode == aco_opcode::v_fma_mixhi_f16) - return instr->valu().opsel_hi[index] ? 16 : 32; - else if (instr->isVALU() || instr->isSALU()) - return instr_info.alu_opcode_infos[(int)instr->opcode].op_types[index].constant_bits(); - else - return 0; + assert(alu->isVALU() || alu->isSALU()); + aco_type type = instr_info.alu_opcode_infos[(int)alu->opcode].op_types[index]; + + if (alu->opcode == aco_opcode::v_fma_mix_f32 || alu->opcode == aco_opcode::v_fma_mixlo_f16 || + alu->opcode == aco_opcode::v_fma_mixhi_f16) + type.bit_size = alu->valu().opsel_hi[index] ? 16 : 32; + + return type; } bool diff --git a/src/amd/compiler/aco_ir.h b/src/amd/compiler/aco_ir.h index 384ea5e1a44..cee83828b75 100644 --- a/src/amd/compiler/aco_ir.h +++ b/src/amd/compiler/aco_ir.h @@ -1899,8 +1899,6 @@ unsigned get_mimg_nsa_dwords(const Instruction* instr); unsigned get_vopd_opy_start(const Instruction* instr); -unsigned get_operand_size(aco_ptr& instr, unsigned index); - bool should_form_clause(const Instruction* a, const Instruction* b); enum vmem_type : uint8_t { @@ -2402,6 +2400,8 @@ struct aco_type { } }; +aco_type get_operand_type(aco_ptr& alu, unsigned index); + struct aco_alu_opcode_info { uint8_t num_operands : 3; uint8_t num_defs : 2; diff --git a/src/amd/compiler/aco_optimizer.cpp b/src/amd/compiler/aco_optimizer.cpp index dfd02d9640e..f92865b68a4 100644 --- a/src/amd/compiler/aco_optimizer.cpp +++ b/src/amd/compiler/aco_optimizer.cpp @@ -774,7 +774,7 @@ propagate_constants_vop3p(opt_ctx& ctx, aco_ptr& instr, ssa_info& i return; assert(instr->operands[i].isTemp()); - unsigned bits = get_operand_size(instr, i); + unsigned bits = get_operand_type(instr, i).constant_bits(); if (info.is_constant(bits)) { instr->operands[i] = get_constant_op(ctx, info, bits); return; @@ -1288,7 +1288,7 @@ label_instruction(opt_ctx& ctx, aco_ptr& instr) /* SALU: propagate inline constants */ else if (instr->isSALU()) { - unsigned bits = get_operand_size(instr, i); + unsigned bits = get_operand_type(instr, i).constant_bits(); if (info.is_constant(bits) && alu_can_accept_constant(instr, i)) { instr->operands[i] = get_constant_op(ctx, info, bits); continue; @@ -1329,7 +1329,7 @@ label_instruction(opt_ctx& ctx, aco_ptr& instr) else can_use_mod &= instr->isDPP16() || can_use_VOP3(ctx, instr); - unsigned bits = get_operand_size(instr, i); + unsigned bits = get_operand_type(instr, i).constant_bits(); can_use_mod &= instr->operands[i].bytes() * 8 == bits; if (info.is_neg() && can_use_mod && @@ -3603,7 +3603,7 @@ combine_mad_mix(opt_ctx& ctx, aco_ptr& instr) continue; } - if (get_operand_size(instr, i) != 32) + if (get_operand_type(instr, i).constant_bits() != 32) continue; /* Conversion to VOP3P will add inline constant operands, but that shouldn't affect @@ -3853,7 +3853,8 @@ combine_instruction(opt_ctx& ctx, aco_ptr& instr) if (is_add_mix && info.parent_instr->definitions[0].bytes() == 2) continue; - if (get_operand_size(instr, i) != info.parent_instr->definitions[0].bytes() * 8) + if (get_operand_type(instr, i).constant_bits() != + info.parent_instr->definitions[0].bytes() * 8) continue; bool legacy = info.parent_instr->opcode == aco_opcode::v_mul_legacy_f32; @@ -4409,7 +4410,7 @@ select_instruction(opt_ctx& ctx, aco_ptr& instr) Operand& op = instr->operands[i]; if (!op.isTemp()) continue; - if (ctx.info[op.tempId()].is_literal(get_operand_size(instr, i))) { + if (ctx.info[op.tempId()].is_literal(get_operand_type(instr, i).constant_bits())) { uint32_t new_literal = ctx.info[op.tempId()].val; float value = uif(new_literal); uint16_t fp16_val = _mesa_float_to_half(value); @@ -4559,7 +4560,7 @@ select_instruction(opt_ctx& ctx, aco_ptr& instr) continue; bool input_mods = can_use_input_modifiers(ctx.program->gfx_level, instr->opcode, 0) && - get_operand_size(instr, 0) == 32; + get_operand_type(instr, 0).constant_bits() == 32; bool mov_uses_mods = info.parent_instr->valu().neg[0] || info.parent_instr->valu().abs[0]; if (((dpp8 && ctx.program->gfx_level < GFX11) || !input_mods) && mov_uses_mods) continue; @@ -4643,7 +4644,7 @@ select_instruction(opt_ctx& ctx, aco_ptr& instr) /* choose a literal to apply */ for (unsigned i = 0; i < num_operands; i++) { Operand op = instr->operands[i]; - unsigned bits = get_operand_size(instr, i); + unsigned bits = get_operand_type(instr, i).constant_bits(); if (instr->isVALU() && op.isTemp() && op.getTemp().type() == RegType::sgpr && op.tempId() != sgpr_ids[0]) @@ -4929,7 +4930,7 @@ apply_literals(opt_ctx& ctx, aco_ptr& instr) if (instr->isSALU() || instr->isVALU()) { for (unsigned i = 0; i < instr->operands.size(); i++) { Operand op = instr->operands[i]; - unsigned bits = get_operand_size(instr, i); + unsigned bits = get_operand_type(instr, i).constant_bits(); if (op.isTemp() && ctx.info[op.tempId()].is_literal(bits) && ctx.uses[op.tempId()] == 0) { Operand literal = Operand::literal32(ctx.info[op.tempId()].val); instr->format = withoutDPP(instr->format); diff --git a/src/amd/compiler/aco_optimizer_postRA.cpp b/src/amd/compiler/aco_optimizer_postRA.cpp index a07703c31bb..258eda91e4f 100644 --- a/src/amd/compiler/aco_optimizer_postRA.cpp +++ b/src/amd/compiler/aco_optimizer_postRA.cpp @@ -638,7 +638,7 @@ try_combine_dpp(pr_opt_ctx& ctx, aco_ptr& instr) continue; bool input_mods = can_use_input_modifiers(ctx.program->gfx_level, instr->opcode, i) && - get_operand_size(instr, i) == 32; + get_operand_type(instr, i).constant_bits() == 32; bool mov_uses_mods = mov->valu().neg[0] || mov->valu().abs[0]; if (((dpp8 && ctx.program->gfx_level < GFX11) || !input_mods) && mov_uses_mods) continue;