diff --git a/src/amd/vulkan/radv_shader.h b/src/amd/vulkan/radv_shader.h index 9cb08415f40..11d7e069cc8 100644 --- a/src/amd/vulkan/radv_shader.h +++ b/src/amd/vulkan/radv_shader.h @@ -188,6 +188,7 @@ enum radv_ud_index { AC_UD_CS_MAX_UD, AC_UD_GS_MAX_UD, AC_UD_TCS_OFFCHIP_LAYOUT = AC_UD_VS_MAX_UD, + AC_UD_TCS_EPILOG_PC, AC_UD_TCS_MAX_UD, AC_UD_TES_STATE = AC_UD_SHADER_START, AC_UD_TES_MAX_UD, diff --git a/src/amd/vulkan/radv_shader_args.c b/src/amd/vulkan/radv_shader_args.c index a68a96981b1..37e3b6054b2 100644 --- a/src/amd/vulkan/radv_shader_args.c +++ b/src/amd/vulkan/radv_shader_args.c @@ -530,6 +530,10 @@ declare_shader_args(const struct radv_device *device, const struct radv_pipeline add_ud_arg(args, 1, AC_ARG_INT, &args->tcs_offchip_layout, AC_UD_TCS_OFFCHIP_LAYOUT); } + if (info->has_epilog) { + add_ud_arg(args, 1, AC_ARG_INT, &args->tcs_epilog_pc, AC_UD_TCS_EPILOG_PC); + } + ac_add_arg(&args->ac, AC_ARG_VGPR, 1, AC_ARG_INT, &args->ac.tcs_patch_id); ac_add_arg(&args->ac, AC_ARG_VGPR, 1, AC_ARG_INT, &args->ac.tcs_rel_ids); @@ -545,6 +549,10 @@ declare_shader_args(const struct radv_device *device, const struct radv_pipeline add_ud_arg(args, 1, AC_ARG_INT, &args->tcs_offchip_layout, AC_UD_TCS_OFFCHIP_LAYOUT); } + if (info->has_epilog) { + add_ud_arg(args, 1, AC_ARG_INT, &args->tcs_epilog_pc, AC_UD_TCS_EPILOG_PC); + } + ac_add_arg(&args->ac, AC_ARG_SGPR, 1, AC_ARG_INT, &args->ac.tess_offchip_offset); ac_add_arg(&args->ac, AC_ARG_SGPR, 1, AC_ARG_INT, &args->ac.tcs_factor_offset); if (args->explicit_scratch_args) { diff --git a/src/amd/vulkan/radv_shader_args.h b/src/amd/vulkan/radv_shader_args.h index 94a30159bd6..b9be54aa62c 100644 --- a/src/amd/vulkan/radv_shader_args.h +++ b/src/amd/vulkan/radv_shader_args.h @@ -68,6 +68,7 @@ struct radv_shader_args { * # [6:13] = the number of tessellation patches */ struct ac_arg tcs_offchip_layout; + struct ac_arg tcs_epilog_pc; /* TES */ /* # [0:7] = the number of tessellation patches