diff --git a/src/intel/compiler/brw_builder.h b/src/intel/compiler/brw_builder.h
index 577f595b626..4357085e5a3 100644
--- a/src/intel/compiler/brw_builder.h
+++ b/src/intel/compiler/brw_builder.h
@@ -632,6 +632,12 @@ public:
 #undef _ALU1
    /** @} */
 
+   brw_inst *
+   SEND() const
+   {
+      return emit(SHADER_OPCODE_SEND, SEND_NUM_SRCS);
+   }
+
    brw_inst *
    ADD(const brw_reg &dst, const brw_reg &src0, const brw_reg &src1) const
    {
diff --git a/src/intel/compiler/brw_compile_fs.cpp b/src/intel/compiler/brw_compile_fs.cpp
index dd10fdd830f..b3afcde54a5 100644
--- a/src/intel/compiler/brw_compile_fs.cpp
+++ b/src/intel/compiler/brw_compile_fs.cpp
@@ -648,7 +648,7 @@ brw_emit_repclear_shader(brw_shader &s)
       if (i > 0)
          bld.uniform().MOV(component(header, 2), brw_imm_ud(i));
 
-      write = bld.emit(SHADER_OPCODE_SEND, SEND_NUM_SRCS);
+      write = bld.SEND();
 
       /* We can use a headerless message for the first render target */
       write->header_size = i == 0 ? 0 : 2;
diff --git a/src/intel/compiler/brw_from_nir.cpp b/src/intel/compiler/brw_from_nir.cpp
index 230edc9df49..cfdcb9d2a71 100644
--- a/src/intel/compiler/brw_from_nir.cpp
+++ b/src/intel/compiler/brw_from_nir.cpp
@@ -4952,13 +4952,15 @@ emit_rt_lsc_fence(const brw_builder &bld,
 
    const brw_builder ubld = bld.exec_all().group(8, 0);
    brw_reg tmp = ubld.vgrf(BRW_TYPE_UD);
-   brw_reg srcs[SEND_NUM_SRCS] = {
-      [SEND_SRC_DESC]     = brw_imm_ud(0),
-      [SEND_SRC_EX_DESC]  = brw_imm_ud(0),
-      [SEND_SRC_PAYLOAD1] = brw_vec8_grf(0, 0),
-      [SEND_SRC_PAYLOAD2] = brw_reg(),
-   };
-   brw_inst *send = ubld.emit(SHADER_OPCODE_SEND, tmp, srcs, SEND_NUM_SRCS);
+
+   brw_inst *send = ubld.SEND();
+   send->dst = tmp;
+
+   send->src[SEND_SRC_DESC]     = brw_imm_ud(0);
+   send->src[SEND_SRC_EX_DESC]  = brw_imm_ud(0);
+   send->src[SEND_SRC_PAYLOAD1] = brw_vec8_grf(0, 0);
+   send->src[SEND_SRC_PAYLOAD2] = brw_reg();
+
    send->sfid = BRW_SFID_UGM;
    send->desc = lsc_fence_msg_desc(devinfo, scope, flush_type, true);
    send->mlen = reg_unit(devinfo); /* g0 header */
diff --git a/src/intel/compiler/brw_reg_allocate.cpp b/src/intel/compiler/brw_reg_allocate.cpp
index dba7cb5ef6b..a2afffbcc10 100644
--- a/src/intel/compiler/brw_reg_allocate.cpp
+++ b/src/intel/compiler/brw_reg_allocate.cpp
@@ -908,13 +908,6 @@ brw_reg_alloc::emit_unspill(const brw_builder &bld,
             offset = build_lane_offsets(ubld, spill_offset, ip);
          }
 
-         brw_reg srcs[SEND_NUM_SRCS] = {
-            [SEND_SRC_DESC] = brw_imm_ud(0),
-            [SEND_SRC_EX_DESC] = build_ex_desc(bld, reg_size, true),
-            [SEND_SRC_PAYLOAD1] = offset,
-            [SEND_SRC_PAYLOAD2] = brw_reg(),
-         };
-
          uint32_t desc = lsc_msg_desc(devinfo, LSC_OP_LOAD,
                                       LSC_ADDR_SURFTYPE_SS,
                                       LSC_ADDR_SIZE_A32,
@@ -923,9 +916,16 @@ brw_reg_alloc::emit_unspill(const brw_builder &bld,
                                       use_transpose,
                                       LSC_CACHE(devinfo, LOAD, L1STATE_L3MOCS));
 
+         const brw_reg ex_desc_reg = build_ex_desc(bld, reg_size, true);
+
+         unspill_inst = ubld.SEND();
+         unspill_inst->dst = dst;
+
+         unspill_inst->src[SEND_SRC_DESC]     = brw_imm_ud(0);
+         unspill_inst->src[SEND_SRC_EX_DESC]  = ex_desc_reg;
+         unspill_inst->src[SEND_SRC_PAYLOAD1] = offset;
+         unspill_inst->src[SEND_SRC_PAYLOAD2] = brw_reg();
 
-         unspill_inst = ubld.emit(SHADER_OPCODE_SEND, dst,
-                                  srcs, ARRAY_SIZE(srcs));
          unspill_inst->sfid = BRW_SFID_UGM;
          unspill_inst->header_size = 0;
          unspill_inst->mlen = lsc_msg_addr_len(devinfo, LSC_ADDR_SIZE_A32,
@@ -947,14 +947,14 @@ brw_reg_alloc::emit_unspill(const brw_builder &bld,
 
          const unsigned bti = GFX8_BTI_STATELESS_NON_COHERENT;
 
-         brw_reg srcs[SEND_NUM_SRCS] = {
-            [SEND_SRC_DESC]     = brw_imm_ud(0),
-            [SEND_SRC_EX_DESC]  = brw_imm_ud(0),
-            [SEND_SRC_PAYLOAD1] = header,
-            [SEND_SRC_PAYLOAD2] = brw_reg(),
-         };
-         unspill_inst = bld.emit(SHADER_OPCODE_SEND, dst,
-                                 srcs, ARRAY_SIZE(srcs));
+         unspill_inst = bld.SEND();
+         unspill_inst->dst = dst;
+
+         unspill_inst->src[SEND_SRC_DESC]     = brw_imm_ud(0);
+         unspill_inst->src[SEND_SRC_EX_DESC]  = brw_imm_ud(0);
+         unspill_inst->src[SEND_SRC_PAYLOAD1] = header;
+         unspill_inst->src[SEND_SRC_PAYLOAD2] = brw_reg();
+
          unspill_inst->mlen = 1;
          unspill_inst->header_size = 1;
          unspill_inst->size_written = reg_size * REG_SIZE;
@@ -996,14 +996,16 @@ brw_reg_alloc::emit_spill(const brw_builder &bld,
       if (devinfo->verx10 >= 125) {
          brw_reg offset = build_lane_offsets(bld, spill_offset, ip);
 
-         brw_reg srcs[SEND_NUM_SRCS] = {
-            [SEND_SRC_DESC]     = brw_imm_ud(0),
-            [SEND_SRC_EX_DESC]  = build_ex_desc(bld, reg_size, false),
-            [SEND_SRC_PAYLOAD1] = offset,
-            [SEND_SRC_PAYLOAD2] = src,
-         };
-         spill_inst = bld.emit(SHADER_OPCODE_SEND, bld.null_reg_f(),
-                               srcs, ARRAY_SIZE(srcs));
+         const brw_reg ex_desc_reg = build_ex_desc(bld, reg_size, false);
+
+         spill_inst = bld.SEND();
+         spill_inst->dst = bld.null_reg_f();
+
+         spill_inst->src[SEND_SRC_DESC]     = brw_imm_ud(0);
+         spill_inst->src[SEND_SRC_EX_DESC]  = ex_desc_reg;
+         spill_inst->src[SEND_SRC_PAYLOAD1] = offset;
+         spill_inst->src[SEND_SRC_PAYLOAD2] = src;
+
          spill_inst->sfid = BRW_SFID_UGM;
          uint32_t desc = lsc_msg_desc(devinfo, LSC_OP_STORE,
                                       LSC_ADDR_SURFTYPE_SS,
@@ -1030,14 +1032,15 @@ brw_reg_alloc::emit_spill(const brw_builder &bld,
          brw_reg header = build_legacy_scratch_header(bld, spill_offset, ip);
 
          const unsigned bti = GFX8_BTI_STATELESS_NON_COHERENT;
-         brw_reg srcs[SEND_NUM_SRCS] = {
-            [SEND_SRC_DESC]     = brw_imm_ud(0),
-            [SEND_SRC_EX_DESC]  = brw_imm_ud(0),
-            [SEND_SRC_PAYLOAD1] = header,
-            [SEND_SRC_PAYLOAD2] = src
-         };
-         spill_inst = bld.emit(SHADER_OPCODE_SEND, bld.null_reg_f(),
-                               srcs, ARRAY_SIZE(srcs));
+
+         spill_inst = bld.SEND();
+         spill_inst->dst = bld.null_reg_f();
+
+         spill_inst->src[SEND_SRC_DESC]     = brw_imm_ud(0);
+         spill_inst->src[SEND_SRC_EX_DESC]  = brw_imm_ud(0);
+         spill_inst->src[SEND_SRC_PAYLOAD1] = header;
+         spill_inst->src[SEND_SRC_PAYLOAD2] = src;
+
          spill_inst->mlen = 1;
          spill_inst->ex_mlen = reg_size;
          spill_inst->size_written = 0;
diff --git a/src/intel/compiler/brw_shader.cpp b/src/intel/compiler/brw_shader.cpp
index e455a3ee0ba..79234735f8f 100644
--- a/src/intel/compiler/brw_shader.cpp
+++ b/src/intel/compiler/brw_shader.cpp
@@ -375,15 +375,12 @@ brw_shader::emit_cs_terminate()
    if (devinfo->ver < 11)
       desc |= (1 << 4); /* Do not dereference URB */
 
-   brw_reg srcs[SEND_NUM_SRCS] = {
-      [SEND_SRC_DESC]     = brw_imm_ud(desc),
-      [SEND_SRC_EX_DESC]  = brw_imm_ud(0),
-      [SEND_SRC_PAYLOAD1] = payload,
-      [SEND_SRC_PAYLOAD2] = brw_reg(),
-   };
-
-   brw_inst *send =
-      ubld.emit(SHADER_OPCODE_SEND, reg_undef, srcs, SEND_NUM_SRCS);
+   brw_inst *send = ubld.SEND();
+   send->dst = reg_undef;
+   send->src[SEND_SRC_DESC]     = brw_imm_ud(desc);
+   send->src[SEND_SRC_EX_DESC]  = brw_imm_ud(0);
+   send->src[SEND_SRC_PAYLOAD1] = payload;
+   send->src[SEND_SRC_PAYLOAD2] = brw_reg();
 
    /* On Alchemist and later, send an EOT message to the message gateway to
     * terminate a compute shader.  For older GPUs, send to the thread spawner.
@@ -684,16 +681,14 @@ brw_shader::assign_curb_setup()
             addr = base_addr;
          }
 
-         brw_reg srcs[SEND_NUM_SRCS] = {
-            [SEND_SRC_DESC]     = brw_imm_ud(0),
-            [SEND_SRC_EX_DESC]  = brw_imm_ud(0),
-            [SEND_SRC_PAYLOAD1] = addr,
-            [SEND_SRC_PAYLOAD2] = brw_reg(),
-         };
+         brw_inst *send = ubld.SEND();
+         send->dst = retype(brw_vec8_grf(payload().num_regs + i, 0),
+                            BRW_TYPE_UD);
 
-         brw_reg dest = retype(brw_vec8_grf(payload().num_regs + i, 0),
-                              BRW_TYPE_UD);
-         brw_inst *send = ubld.emit(SHADER_OPCODE_SEND, dest, srcs, 4);
+         send->src[SEND_SRC_DESC]     = brw_imm_ud(0);
+         send->src[SEND_SRC_EX_DESC]  = brw_imm_ud(0);
+         send->src[SEND_SRC_PAYLOAD1] = addr;
+         send->src[SEND_SRC_PAYLOAD2] = brw_reg();
 
          send->sfid = BRW_SFID_UGM;
          uint32_t desc = lsc_msg_desc(devinfo, LSC_OP_LOAD,
diff --git a/src/intel/compiler/brw_workaround.cpp b/src/intel/compiler/brw_workaround.cpp
index c486ee105cb..ce8fdb12223 100644
--- a/src/intel/compiler/brw_workaround.cpp
+++ b/src/intel/compiler/brw_workaround.cpp
@@ -106,7 +106,7 @@ brw_workaround_memory_fence_before_eot(brw_shader &s)
       const brw_builder ubld = brw_builder(inst).uniform();
 
       brw_reg dst = ubld.vgrf(BRW_TYPE_UD);
-      brw_inst *dummy_fence = ubld.emit(SHADER_OPCODE_SEND, SEND_NUM_SRCS);
+      brw_inst *dummy_fence = ubld.SEND();
 
       dummy_fence->src[SEND_SRC_DESC]     = brw_imm_ud(0);
       dummy_fence->src[SEND_SRC_EX_DESC]  = brw_imm_ud(0);
diff --git a/src/intel/compiler/test_lower_scoreboard.cpp b/src/intel/compiler/test_lower_scoreboard.cpp
index baf0c57d3de..d79a37a5207 100644
--- a/src/intel/compiler/test_lower_scoreboard.cpp
+++ b/src/intel/compiler/test_lower_scoreboard.cpp
@@ -43,15 +43,19 @@ emit_SEND(const brw_builder &bld, const brw_reg &dst,
           const brw_reg &desc, const brw_reg &payload)
 {
    brw_reg uniform_desc = component(desc, 0);
-   brw_reg srcs[SEND_NUM_SRCS] = {
-      [SEND_SRC_DESC]     = uniform_desc,
-      [SEND_SRC_EX_DESC]  = uniform_desc,
-      [SEND_SRC_PAYLOAD1] = payload,
-      [SEND_SRC_PAYLOAD2] = brw_reg(),
-   };
-   brw_inst *inst = bld.emit(SHADER_OPCODE_SEND, dst, srcs, SEND_NUM_SRCS);
-   inst->mlen = 1;
-   return inst;
+
+   brw_inst *send = bld.SEND();
+   send->dst = dst;
+
+   send->src[SEND_SRC_DESC]     = uniform_desc;
+   send->src[SEND_SRC_EX_DESC]  = uniform_desc;
+   send->src[SEND_SRC_PAYLOAD1] = payload;
+   send->src[SEND_SRC_PAYLOAD2] = brw_reg();
+
+   send->mlen = 1;
+   send->size_written = dst.component_size(send->exec_size);
+
+   return send;
 }
 
 bool operator ==(const tgl_swsb &a, const tgl_swsb &b)