diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c
index 7c499dc66fc..65d0870ad55 100644
--- a/src/amd/vulkan/radv_cmd_buffer.c
+++ b/src/amd/vulkan/radv_cmd_buffer.c
@@ -484,9 +484,6 @@ radv_reset_cmd_buffer(struct vk_command_buffer *vk_cmd_buffer, UNUSED VkCommandB
       radv_cs_add_buffer(device->ws, cmd_buffer->cs, cmd_buffer->upload.upload_bo);
    cmd_buffer->upload.offset = 0;
 
-   memset(cmd_buffer->vertex_binding_buffers, 0, sizeof(struct radv_buffer *) * cmd_buffer->used_vertex_bindings);
-   cmd_buffer->used_vertex_bindings = 0;
-
    for (unsigned i = 0; i < MAX_BIND_POINTS; i++) {
       cmd_buffer->descriptors[i].dirty = 0;
       cmd_buffer->descriptors[i].valid = 0;
@@ -4892,14 +4889,14 @@ lookup_vs_prolog(struct radv_cmd_buffer *cmd_buffer, const struct radv_shader *v
 
          uint8_t format_req = vi_state->format_align_req_minus_1[index];
          uint8_t component_req = vi_state->component_align_req_minus_1[index];
-         uint64_t vb_offset = cmd_buffer->vertex_bindings[binding].offset;
+         uint64_t vb_addr = cmd_buffer->vertex_bindings[binding].addr;
          uint64_t vb_stride = cmd_buffer->vertex_bindings[binding].stride;
 
-         VkDeviceSize offset = vb_offset + vi_state->offsets[index];
+         VkDeviceSize addr = vb_addr + vi_state->offsets[index];
 
-         if (misalignment_possible && ((offset | vb_stride) & format_req))
+         if (misalignment_possible && ((addr | vb_stride) & format_req))
             misaligned_mask |= BITFIELD_BIT(index);
-         if ((offset | vb_stride) & component_req)
+         if ((addr | vb_stride) & component_req)
             unaligned_mask |= BITFIELD_BIT(index);
       }
       cmd_buffer->state.vbo_misaligned_mask = misaligned_mask;
@@ -6972,9 +6969,6 @@ radv_CmdBindVertexBuffers2(VkCommandBuffer commandBuffer, uint32_t firstBinding,
 
    assert(firstBinding + bindingCount <= MAX_VBS);
 
-   if (firstBinding + bindingCount > cmd_buffer->used_vertex_bindings)
-      cmd_buffer->used_vertex_bindings = firstBinding + bindingCount;
-
    uint32_t misaligned_mask_invalid = 0;
 
    for (uint32_t i = 0; i < bindingCount; i++) {
@@ -6983,21 +6977,20 @@ radv_CmdBindVertexBuffers2(VkCommandBuffer commandBuffer, uint32_t firstBinding,
       VkDeviceSize size = pSizes ? pSizes[i] : VK_WHOLE_SIZE;
       /* if pStrides=NULL, it shouldn't overwrite the strides specified by CmdSetVertexInputEXT */
       VkDeviceSize stride = pStrides ? pStrides[i] : vb[idx].stride;
+      uint64_t addr = buffer ? buffer->addr + pOffsets[i] : 0;
 
-      if (!!cmd_buffer->vertex_binding_buffers[idx] != !!buffer ||
-          (buffer && ((vb[idx].offset & 0x3) != (pOffsets[i] & 0x3) || (vb[idx].stride & 0x3) != (stride & 0x3)))) {
+      if (!!vb[idx].addr != !!addr ||
+          (addr && (((vb[idx].addr & 0x3) != (addr & 0x3) || (vb[idx].stride & 0x3) != (stride & 0x3))))) {
          misaligned_mask_invalid |= vi_state->bindings_match_attrib ? BITFIELD_BIT(idx) : 0xffffffff;
       }
 
-      cmd_buffer->vertex_binding_buffers[idx] = buffer;
-      vb[idx].offset = pOffsets[i];
-      vb[idx].addr = buffer ? buffer->addr + pOffsets[i] : 0;
+      vb[idx].addr = addr;
       vb[idx].size = buffer ? vk_buffer_range(&buffer->vk, pOffsets[i], size) : 0;
       vb[idx].stride = stride;
 
       uint32_t bit = BITFIELD_BIT(idx);
       if (buffer) {
-         radv_cs_add_buffer(device->ws, cmd_buffer->cs, cmd_buffer->vertex_binding_buffers[idx]->bo);
+         radv_cs_add_buffer(device->ws, cmd_buffer->cs, buffer->bo);
          cmd_buffer->state.vbo_bound_mask |= bit;
       } else {
          cmd_buffer->state.vbo_bound_mask &= ~bit;
@@ -8448,10 +8441,10 @@ radv_CmdSetVertexInputEXT(VkCommandBuffer commandBuffer, uint32_t vertexBindingD
 
       if (state->vbo_bound_mask & BITFIELD_BIT(attrib->binding)) {
          uint32_t stride = binding->stride;
-         uint64_t offset = cmd_buffer->vertex_bindings[attrib->binding].offset + vi_state->offsets[loc];
-         if ((chip == GFX6 || chip >= GFX10) && ((stride | offset) & format_align_req_minus_1))
+         uint64_t addr = cmd_buffer->vertex_bindings[attrib->binding].addr + vi_state->offsets[loc];
+         if ((chip == GFX6 || chip >= GFX10) && ((stride | addr) & format_align_req_minus_1))
             state->vbo_misaligned_mask |= BITFIELD_BIT(loc);
-         if ((stride | offset) & component_align_req_minus_1)
+         if ((stride | addr) & component_align_req_minus_1)
             state->vbo_unaligned_mask |= BITFIELD_BIT(loc);
       }
    }
diff --git a/src/amd/vulkan/radv_cmd_buffer.h b/src/amd/vulkan/radv_cmd_buffer.h
index 1b06bf6268c..04fb87d03d1 100644
--- a/src/amd/vulkan/radv_cmd_buffer.h
+++ b/src/amd/vulkan/radv_cmd_buffer.h
@@ -145,7 +145,6 @@ enum radv_cmd_flush_bits {
 
 struct radv_vertex_binding {
    uint64_t addr;
-   VkDeviceSize offset;
    VkDeviceSize size;
    VkDeviceSize stride;
 };
@@ -521,9 +520,7 @@ struct radv_cmd_buffer {
    VkCommandBufferUsageFlags usage_flags;
    struct radeon_cmdbuf *cs;
    struct radv_cmd_state state;
-   struct radv_buffer *vertex_binding_buffers[MAX_VBS];
    struct radv_vertex_binding vertex_bindings[MAX_VBS];
-   uint32_t used_vertex_bindings;
    struct radv_streamout_binding streamout_bindings[MAX_SO_BUFFERS];
    enum radv_queue_family qf;