From f800af2231401641abed2a6d90a9fc22ba5ef60f Mon Sep 17 00:00:00 2001 From: Rhys Perry Date: Fri, 25 Feb 2022 17:40:16 +0000 Subject: [PATCH] ac/nir: remove TCS nir_var_shader_out memory barrier MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit nir_var_shader_out writes are only used for later TES invocations, so I don't think there's any need for the TCS workgroup to wait for them. fossil-db (Sienna Cichlid): Totals from 1691 (1.04% of 162293) affected shaders: Instrs: 710699 -> 709008 (-0.24%) CodeSize: 3830168 -> 3823404 (-0.18%) Latency: 3396997 -> 3007934 (-11.45%) InvThroughput: 1212094 -> 1082823 (-10.67%) Signed-off-by: Rhys Perry Reviewed-by: Timur Kristóf Part-of: --- src/amd/common/ac_nir_lower_tess_io_to_mem.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/amd/common/ac_nir_lower_tess_io_to_mem.c b/src/amd/common/ac_nir_lower_tess_io_to_mem.c index dd2951d71f0..3d363f4582c 100644 --- a/src/amd/common/ac_nir_lower_tess_io_to_mem.c +++ b/src/amd/common/ac_nir_lower_tess_io_to_mem.c @@ -505,7 +505,7 @@ hs_emit_write_tess_factors(nir_shader *shader, b->cursor = nir_after_block(last_block); nir_scoped_barrier(b, .execution_scope=NIR_SCOPE_WORKGROUP, .memory_scope=NIR_SCOPE_WORKGROUP, - .memory_semantics=NIR_MEMORY_ACQ_REL, .memory_modes=nir_var_shader_out|nir_var_mem_shared); + .memory_semantics=NIR_MEMORY_ACQ_REL, .memory_modes=nir_var_mem_shared); nir_ssa_def *invocation_id = nir_load_invocation_id(b);