From f7b29d792464b0224ae5155d15d48ab8e55840cb Mon Sep 17 00:00:00 2001
From: Kenneth Graunke <kenneth@whitecape.org>
Date: Mon, 9 Jan 2023 15:57:14 -0800
Subject: [PATCH] intel/compiler: Drop redundant 32-bit expansion for shared
 float atomics

We already expanded data to 32-bit a few lines earlier, so this is just
redundantly doing it a second time.

Fixes: 43169dbbe5f ("intel/compiler: Support 16 bit float ops")
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Rohan Garg <rohan.garg@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20604>
---
 src/intel/compiler/brw_fs_nir.cpp | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/intel/compiler/brw_fs_nir.cpp b/src/intel/compiler/brw_fs_nir.cpp
index cc2d3221cb2..990c5ea4ce7 100644
--- a/src/intel/compiler/brw_fs_nir.cpp
+++ b/src/intel/compiler/brw_fs_nir.cpp
@@ -6091,7 +6091,7 @@ fs_visitor::nir_emit_shared_atomic(const fs_builder &bld,
    if (op == LSC_OP_ATOMIC_CMPXCHG) {
       fs_reg tmp = bld.vgrf(data.type, 2);
       fs_reg sources[2] = {
-         expand_to_32bit(bld, data),
+         data,
          expand_to_32bit(bld, get_nir_src(instr->src[2]))
       };
       bld.LOAD_PAYLOAD(tmp, sources, 2, 0);