From f7acdb1d1d7f817b96521bf97137eedf84b2dd03 Mon Sep 17 00:00:00 2001
From: Dave Airlie <airlied@redhat.com>
Date: Thu, 25 Mar 2021 13:40:51 +1000
Subject: [PATCH] st/glthread: allow for invalid L3 cache id.
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If we get 0xffffffff consider L3 cache info invalid and
don't continue.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/4496
Fixes: d8ea5099658 ("util: completely rewrite and do AMD Zen L3 cache pinning correctly")
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9782>
---
 src/mesa/main/glthread.c         | 13 +++++++------
 src/mesa/state_tracker/st_draw.c | 10 ++++++----
 src/util/u_cpu_detect.c          |  2 ++
 src/util/u_cpu_detect.h          |  2 ++
 4 files changed, 17 insertions(+), 10 deletions(-)

diff --git a/src/mesa/main/glthread.c b/src/mesa/main/glthread.c
index 0267165cf45..ace921333b3 100644
--- a/src/mesa/main/glthread.c
+++ b/src/mesa/main/glthread.c
@@ -223,12 +223,13 @@ _mesa_glthread_flush_batch(struct gl_context *ctx)
       int cpu = util_get_current_cpu();
 
       if (cpu >= 0) {
-         unsigned L3_cache = util_get_cpu_caps()->cpu_to_L3[cpu];
-
-         util_set_thread_affinity(glthread->queue.threads[0],
-                                  util_get_cpu_caps()->L3_affinity_mask[L3_cache],
-                                  NULL, util_get_cpu_caps()->num_cpu_mask_bits);
-         ctx->Driver.PinDriverToL3Cache(ctx, L3_cache);
+         uint16_t L3_cache = util_get_cpu_caps()->cpu_to_L3[cpu];
+         if (L3_cache != U_CPU_INVALID_L3) {
+            util_set_thread_affinity(glthread->queue.threads[0],
+                                     util_get_cpu_caps()->L3_affinity_mask[L3_cache],
+                                     NULL, util_get_cpu_caps()->num_cpu_mask_bits);
+            ctx->Driver.PinDriverToL3Cache(ctx, L3_cache);
+         }
       }
    }
 
diff --git a/src/mesa/state_tracker/st_draw.c b/src/mesa/state_tracker/st_draw.c
index ee7b2ec8517..d9f5fe7aba8 100644
--- a/src/mesa/state_tracker/st_draw.c
+++ b/src/mesa/state_tracker/st_draw.c
@@ -117,11 +117,13 @@ prepare_draw(struct st_context *st, struct gl_context *ctx)
       int cpu = util_get_current_cpu();
       if (cpu >= 0) {
          struct pipe_context *pipe = st->pipe;
-         unsigned L3_cache = util_get_cpu_caps()->cpu_to_L3[cpu];
+         uint16_t L3_cache = util_get_cpu_caps()->cpu_to_L3[cpu];
 
-         pipe->set_context_param(pipe,
-                                 PIPE_CONTEXT_PARAM_PIN_THREADS_TO_L3_CACHE,
-                                 L3_cache);
+         if (L3_cache != U_CPU_INVALID_L3) {
+            pipe->set_context_param(pipe,
+                                    PIPE_CONTEXT_PARAM_PIN_THREADS_TO_L3_CACHE,
+                                    L3_cache);
+         }
       }
    }
 }
diff --git a/src/util/u_cpu_detect.c b/src/util/u_cpu_detect.c
index a2403cd5658..bedb94f22ec 100644
--- a/src/util/u_cpu_detect.c
+++ b/src/util/u_cpu_detect.c
@@ -438,6 +438,8 @@ get_cpu_topology(void)
    util_cpu_caps.cores_per_L3 = util_cpu_caps.nr_cpus;
    util_cpu_caps.num_L3_caches = 1;
 
+   memset(util_cpu_caps.cpu_to_L3, 0xff, sizeof(util_cpu_caps.cpu_to_L3));
+
 #if defined(PIPE_ARCH_X86) || defined(PIPE_ARCH_X86_64)
    /* AMD Zen */
    if (util_cpu_caps.family >= CPU_AMD_ZEN1_ZEN2 &&
diff --git a/src/util/u_cpu_detect.h b/src/util/u_cpu_detect.h
index ec3ef436581..1c7239b2ec7 100644
--- a/src/util/u_cpu_detect.h
+++ b/src/util/u_cpu_detect.h
@@ -105,6 +105,8 @@ struct util_cpu_caps_t {
    util_affinity_mask *L3_affinity_mask;
 };
 
+#define U_CPU_INVALID_L3 0xffff
+
 static inline const struct util_cpu_caps_t *
 util_get_cpu_caps(void)
 {