From f5ec61767743b091e60740a1ec177829a1786682 Mon Sep 17 00:00:00 2001 From: Pierre-Eric Pelloux-Prayer Date: Mon, 27 Jul 2020 19:27:53 +0200 Subject: [PATCH] ac/gpu_info: add detection of TMZ support MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Reviewed-by: Marek Olšák Part-of: --- src/amd/common/ac_gpu_info.c | 37 ++++++++++++++++++++++++++++++++++++ src/amd/common/ac_gpu_info.h | 1 + 2 files changed, 38 insertions(+) diff --git a/src/amd/common/ac_gpu_info.c b/src/amd/common/ac_gpu_info.c index fee83ace6bf..40db254e556 100644 --- a/src/amd/common/ac_gpu_info.c +++ b/src/amd/common/ac_gpu_info.c @@ -140,6 +140,41 @@ static uint32_t get_l2_cache_size(enum radeon_family family) } } +static bool +has_tmz_support(amdgpu_device_handle dev, + struct radeon_info *info, + struct amdgpu_gpu_info *amdinfo) +{ + struct amdgpu_bo_alloc_request request = {0}; + int r; + amdgpu_bo_handle bo; + + if (amdinfo->ids_flags & AMDGPU_IDS_FLAGS_TMZ) + return true; + + /* AMDGPU_IDS_FLAGS_TMZ is supported starting from drm_minor 40 */ + if (info->drm_minor >= 40) + return false; + + /* Find out ourselves if TMZ is enabled */ + if (info->chip_class < GFX9) + return false; + + if (info->drm_minor < 36) + return false; + + request.alloc_size = 256; + request.phys_alignment = 1024; + request.preferred_heap = AMDGPU_GEM_DOMAIN_VRAM; + request.flags = AMDGPU_GEM_CREATE_ENCRYPTED; + r = amdgpu_bo_alloc(dev, &request, &bo); + if (r) + return false; + amdgpu_bo_free(bo); + return true; +} + + bool ac_query_gpu_info(int fd, void *dev_p, struct radeon_info *info, struct amdgpu_gpu_info *amdinfo) { @@ -499,6 +534,7 @@ bool ac_query_gpu_info(int fd, void *dev_p, struct radeon_info *info, info->has_read_registers_query = true; info->has_scheduled_fence_dependency = info->drm_minor >= 28; info->mid_command_buffer_preemption_enabled = amdinfo->ids_flags & AMDGPU_IDS_FLAGS_PREEMPTION; + info->has_tmz_support = has_tmz_support(dev, info, amdinfo); info->pa_sc_tile_steering_override = device_info.pa_sc_tile_steering_override; info->num_render_backends = amdinfo->rb_pipes; @@ -920,6 +956,7 @@ void ac_print_gpu_info(struct radeon_info *info) printf(" has_scheduled_fence_dependency = %u\n", info->has_scheduled_fence_dependency); printf(" mid_command_buffer_preemption_enabled = %u\n", info->mid_command_buffer_preemption_enabled); + printf(" has_tmz_support = %u\n", info->has_tmz_support); printf("Shader core info:\n"); printf(" max_shader_clock = %i\n", info->max_shader_clock); diff --git a/src/amd/common/ac_gpu_info.h b/src/amd/common/ac_gpu_info.h index f6d4e621b58..e24a0bb2c67 100644 --- a/src/amd/common/ac_gpu_info.h +++ b/src/amd/common/ac_gpu_info.h @@ -156,6 +156,7 @@ struct radeon_info { bool has_scheduled_fence_dependency; /* Whether SR-IOV is enabled or amdgpu.mcbp=1 was set on the kernel command line. */ bool mid_command_buffer_preemption_enabled; + bool has_tmz_support; /* Shader cores. */ uint32_t cu_mask[4][2];