radv: add initial non-conformant radv vulkan driver
This squashes all the radv development up until now into one for merging. History can be found: https://github.com/airlied/mesa/tree/semi-interesting This requires llvm 3.9 and is in no way considered a conformant vulkan implementation. It can run a number of vulkan applications, and supports all GPUs using the amdgpu kernel driver. Thanks to Intel for providing anv and spirv->nir, and Emil Velikov for reviewing build integration. Parts of this are: Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com> Acked-by: Edward O'Callaghan <funfunctor@folklore1984.net> Authors: Bas Nieuwenhuizen and Dave Airlie Signed-off-by: Dave Airlie <airlied@redhat.com>
This commit is contained in:
Dave Airlie
@@ -0,0 +1,415 @@
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/*
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* Copyrigh 2016 Red Hat Inc.
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* Based on anv:
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* Copyright © 2015 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*/
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#include <assert.h>
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#include <stdbool.h>
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#include <string.h>
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#include <unistd.h>
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#include <fcntl.h>
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#include "radv_private.h"
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#include "radv_cs.h"
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#include "sid.h"
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static unsigned get_max_db(struct radv_device *device)
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{
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unsigned num_db = device->instance->physicalDevice.rad_info.num_render_backends;
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unsigned rb_mask = device->instance->physicalDevice.rad_info.enabled_rb_mask;
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if (device->instance->physicalDevice.rad_info.chip_class == SI)
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num_db = 8;
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else
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num_db = MAX2(8, num_db);
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/* Otherwise we need to change the query reset procedure */
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assert(rb_mask == ((1ull << num_db) - 1));
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return num_db;
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}
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VkResult radv_CreateQueryPool(
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VkDevice _device,
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const VkQueryPoolCreateInfo* pCreateInfo,
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const VkAllocationCallbacks* pAllocator,
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VkQueryPool* pQueryPool)
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{
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RADV_FROM_HANDLE(radv_device, device, _device);
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uint64_t size;
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struct radv_query_pool *pool = radv_alloc2(&device->alloc, pAllocator,
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sizeof(*pool), 8,
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VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
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if (!pool)
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return VK_ERROR_OUT_OF_HOST_MEMORY;
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switch(pCreateInfo->queryType) {
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case VK_QUERY_TYPE_OCCLUSION:
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/* 16 bytes tmp. buffer as the compute packet writes 64 bits, but
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* the app. may have 32 bits of space. */
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pool->stride = 16 * get_max_db(device) + 16;
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break;
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case VK_QUERY_TYPE_PIPELINE_STATISTICS:
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pool->stride = 16 * 11;
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break;
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case VK_QUERY_TYPE_TIMESTAMP:
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pool->stride = 8;
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break;
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default:
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unreachable("creating unhandled query type");
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}
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pool->type = pCreateInfo->queryType;
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pool->availability_offset = pool->stride * pCreateInfo->queryCount;
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size = pool->availability_offset + 4 * pCreateInfo->queryCount;
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pool->bo = device->ws->buffer_create(device->ws, size,
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64, RADEON_DOMAIN_GTT, 0);
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if (!pool->bo) {
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radv_free2(&device->alloc, pAllocator, pool);
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return VK_ERROR_OUT_OF_DEVICE_MEMORY;
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}
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pool->ptr = device->ws->buffer_map(pool->bo);
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if (!pool->ptr) {
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device->ws->buffer_destroy(pool->bo);
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radv_free2(&device->alloc, pAllocator, pool);
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return VK_ERROR_OUT_OF_DEVICE_MEMORY;
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}
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memset(pool->ptr, 0, size);
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*pQueryPool = radv_query_pool_to_handle(pool);
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return VK_SUCCESS;
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}
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void radv_DestroyQueryPool(
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VkDevice _device,
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VkQueryPool _pool,
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const VkAllocationCallbacks* pAllocator)
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{
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RADV_FROM_HANDLE(radv_device, device, _device);
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RADV_FROM_HANDLE(radv_query_pool, pool, _pool);
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if (!pool)
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return;
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device->ws->buffer_destroy(pool->bo);
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radv_free2(&device->alloc, pAllocator, pool);
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}
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VkResult radv_GetQueryPoolResults(
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VkDevice _device,
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VkQueryPool queryPool,
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uint32_t firstQuery,
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uint32_t queryCount,
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size_t dataSize,
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void* pData,
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VkDeviceSize stride,
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VkQueryResultFlags flags)
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{
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RADV_FROM_HANDLE(radv_query_pool, pool, queryPool);
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char *data = pData;
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VkResult result = VK_SUCCESS;
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for(unsigned i = 0; i < queryCount; ++i, data += stride) {
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char *dest = data;
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unsigned query = firstQuery + i;
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char *src = pool->ptr + query * pool->stride;
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uint32_t available;
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if (flags & VK_QUERY_RESULT_WAIT_BIT) {
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while(!*(volatile uint32_t*)(pool->ptr + pool->availability_offset + 4 * query))
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;
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}
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if (!*(uint32_t*)(pool->ptr + pool->availability_offset + 4 * query) &&
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!(flags & VK_QUERY_RESULT_PARTIAL_BIT)) {
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if (flags & VK_QUERY_RESULT_WITH_AVAILABILITY_BIT)
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*(uint32_t*)dest = 0;
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result = VK_NOT_READY;
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continue;
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}
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available = *(uint32_t*)(pool->ptr + pool->availability_offset + 4 * query);
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switch (pool->type) {
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case VK_QUERY_TYPE_TIMESTAMP:
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if (flags & VK_QUERY_RESULT_64_BIT) {
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*(uint64_t*)dest = *(uint64_t*)src;
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dest += 8;
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} else {
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*(uint32_t*)dest = *(uint32_t*)src;
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dest += 4;
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}
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break;
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case VK_QUERY_TYPE_OCCLUSION: {
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uint64_t result = *(uint64_t*)(src + pool->stride - 16);
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if (flags & VK_QUERY_RESULT_64_BIT) {
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*(uint64_t*)dest = result;
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dest += 8;
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} else {
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*(uint32_t*)dest = result;
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dest += 4;
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}
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break;
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default:
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unreachable("trying to get results of unhandled query type");
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}
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}
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if (flags & VK_QUERY_RESULT_WITH_AVAILABILITY_BIT) {
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*(uint32_t*)dest = available;
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dest += 4;
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}
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}
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return result;
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}
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void radv_CmdCopyQueryPoolResults(
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VkCommandBuffer commandBuffer,
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VkQueryPool queryPool,
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uint32_t firstQuery,
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uint32_t queryCount,
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VkBuffer dstBuffer,
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VkDeviceSize dstOffset,
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VkDeviceSize stride,
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VkQueryResultFlags flags)
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{
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RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
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RADV_FROM_HANDLE(radv_query_pool, pool, queryPool);
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RADV_FROM_HANDLE(radv_buffer, dst_buffer, dstBuffer);
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struct radeon_winsys_cs *cs = cmd_buffer->cs;
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uint64_t va = cmd_buffer->device->ws->buffer_get_va(pool->bo);
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uint64_t dest_va = cmd_buffer->device->ws->buffer_get_va(dst_buffer->bo);
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dest_va += dst_buffer->offset + dstOffset;
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cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, pool->bo, 8);
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cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, dst_buffer->bo, 8);
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for(unsigned i = 0; i < queryCount; ++i, dest_va += stride) {
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unsigned query = firstQuery + i;
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uint64_t local_src_va = va + query * pool->stride;
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unsigned elem_size = (flags & VK_QUERY_RESULT_64_BIT) ? 8 : 4;
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unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 26);
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if (flags & VK_QUERY_RESULT_WAIT_BIT) {
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/* TODO, not sure if there is any case where we won't always be ready yet */
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uint64_t avail_va = va + pool->availability_offset + 4 * query;
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/* This waits on the ME. All copies below are done on the ME */
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radeon_emit(cs, PKT3(PKT3_WAIT_REG_MEM, 5, 0));
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radeon_emit(cs, WAIT_REG_MEM_EQUAL | WAIT_REG_MEM_MEM_SPACE(1));
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radeon_emit(cs, avail_va);
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radeon_emit(cs, avail_va >> 32);
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radeon_emit(cs, 1); /* reference value */
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radeon_emit(cs, 0xffffffff); /* mask */
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radeon_emit(cs, 4); /* poll interval */
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}
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switch (pool->type) {
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case VK_QUERY_TYPE_OCCLUSION:
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local_src_va += pool->stride - 16;
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case VK_QUERY_TYPE_TIMESTAMP:
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radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
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radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
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COPY_DATA_DST_SEL(COPY_DATA_MEM) |
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((flags & VK_QUERY_RESULT_64_BIT) ? COPY_DATA_COUNT_SEL : 0));
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radeon_emit(cs, local_src_va);
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radeon_emit(cs, local_src_va >> 32);
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radeon_emit(cs, dest_va);
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radeon_emit(cs, dest_va >> 32);
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break;
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default:
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unreachable("trying to get results of unhandled query type");
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}
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/* The flag could be still changed while the data copy is busy and we
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* then might have invalid data, but a ready flag. However, the availability
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* writes happen on the ME too, so they should be synchronized. Might need to
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* revisit this with multiple queues.
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*/
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if (flags & VK_QUERY_RESULT_WITH_AVAILABILITY_BIT) {
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uint64_t avail_va = va + pool->availability_offset + 4 * query;
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uint64_t avail_dest_va = dest_va;
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if (pool->type != VK_QUERY_TYPE_PIPELINE_STATISTICS)
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avail_dest_va += elem_size;
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else
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abort();
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radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
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radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
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COPY_DATA_DST_SEL(COPY_DATA_MEM));
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radeon_emit(cs, avail_va);
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radeon_emit(cs, avail_va >> 32);
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radeon_emit(cs, avail_dest_va);
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radeon_emit(cs, avail_dest_va >> 32);
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}
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assert(cs->cdw <= cdw_max);
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}
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}
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void radv_CmdResetQueryPool(
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VkCommandBuffer commandBuffer,
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VkQueryPool queryPool,
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uint32_t firstQuery,
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uint32_t queryCount)
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{
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RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
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RADV_FROM_HANDLE(radv_query_pool, pool, queryPool);
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uint64_t va = cmd_buffer->device->ws->buffer_get_va(pool->bo);
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cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, pool->bo, 8);
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si_cp_dma_clear_buffer(cmd_buffer, va + firstQuery * pool->stride,
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queryCount * pool->stride, 0);
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si_cp_dma_clear_buffer(cmd_buffer, va + pool->availability_offset + firstQuery * 4,
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queryCount * 4, 0);
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}
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void radv_CmdBeginQuery(
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VkCommandBuffer commandBuffer,
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VkQueryPool queryPool,
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uint32_t query,
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VkQueryControlFlags flags)
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{
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RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
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RADV_FROM_HANDLE(radv_query_pool, pool, queryPool);
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struct radeon_winsys_cs *cs = cmd_buffer->cs;
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uint64_t va = cmd_buffer->device->ws->buffer_get_va(pool->bo);
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va += pool->stride * query;
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cmd_buffer->device->ws->cs_add_buffer(cs, pool->bo, 8);
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switch (pool->type) {
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case VK_QUERY_TYPE_OCCLUSION:
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radeon_check_space(cmd_buffer->device->ws, cs, 7);
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++cmd_buffer->state.active_occlusion_queries;
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if (cmd_buffer->state.active_occlusion_queries == 1)
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radv_set_db_count_control(cmd_buffer);
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radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 2, 0));
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radeon_emit(cs, EVENT_TYPE(V_028A90_ZPASS_DONE) | EVENT_INDEX(1));
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radeon_emit(cs, va);
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radeon_emit(cs, va >> 32);
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break;
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default:
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unreachable("beginning unhandled query type");
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}
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}
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void radv_CmdEndQuery(
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VkCommandBuffer commandBuffer,
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VkQueryPool queryPool,
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uint32_t query)
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{
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RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
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RADV_FROM_HANDLE(radv_query_pool, pool, queryPool);
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struct radeon_winsys_cs *cs = cmd_buffer->cs;
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uint64_t va = cmd_buffer->device->ws->buffer_get_va(pool->bo);
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uint64_t avail_va = va + pool->availability_offset + 4 * query;
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va += pool->stride * query;
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cmd_buffer->device->ws->cs_add_buffer(cs, pool->bo, 8);
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switch (pool->type) {
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case VK_QUERY_TYPE_OCCLUSION:
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radeon_check_space(cmd_buffer->device->ws, cs, 14);
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cmd_buffer->state.active_occlusion_queries--;
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if (cmd_buffer->state.active_occlusion_queries == 0)
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radv_set_db_count_control(cmd_buffer);
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radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 2, 0));
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radeon_emit(cs, EVENT_TYPE(V_028A90_ZPASS_DONE) | EVENT_INDEX(1));
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radeon_emit(cs, va + 8);
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radeon_emit(cs, (va + 8) >> 32);
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radeon_emit(cs, PKT3(PKT3_OCCLUSION_QUERY, 3, 0));
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radeon_emit(cs, va);
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radeon_emit(cs, va >> 32);
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radeon_emit(cs, va + pool->stride - 16);
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radeon_emit(cs, (va + pool->stride - 16) >> 32);
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break;
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default:
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unreachable("ending unhandled query type");
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}
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radeon_check_space(cmd_buffer->device->ws, cs, 5);
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radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0));
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radeon_emit(cs, S_370_DST_SEL(V_370_MEMORY_SYNC) |
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S_370_WR_CONFIRM(1) |
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S_370_ENGINE_SEL(V_370_ME));
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radeon_emit(cs, avail_va);
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radeon_emit(cs, avail_va >> 32);
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radeon_emit(cs, 1);
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}
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void radv_CmdWriteTimestamp(
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VkCommandBuffer commandBuffer,
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VkPipelineStageFlagBits pipelineStage,
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VkQueryPool queryPool,
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uint32_t query)
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{
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RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
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RADV_FROM_HANDLE(radv_query_pool, pool, queryPool);
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struct radeon_winsys_cs *cs = cmd_buffer->cs;
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uint64_t va = cmd_buffer->device->ws->buffer_get_va(pool->bo);
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uint64_t avail_va = va + pool->availability_offset + 4 * query;
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uint64_t query_va = va + pool->stride * query;
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cmd_buffer->device->ws->cs_add_buffer(cs, pool->bo, 5);
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unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 11);
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radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOP, 4, 0));
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radeon_emit(cs, EVENT_TYPE(V_028A90_BOTTOM_OF_PIPE_TS) | EVENT_INDEX(5));
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radeon_emit(cs, query_va);
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radeon_emit(cs, (3 << 29) | ((query_va >> 32) & 0xFFFF));
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radeon_emit(cs, 0);
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radeon_emit(cs, 0);
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radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0));
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radeon_emit(cs, S_370_DST_SEL(V_370_MEMORY_SYNC) |
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S_370_WR_CONFIRM(1) |
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S_370_ENGINE_SEL(V_370_ME));
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radeon_emit(cs, avail_va);
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radeon_emit(cs, avail_va >> 32);
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radeon_emit(cs, 1);
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assert(cmd_buffer->cs->cdw <= cdw_max);
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}
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