From f3e2900c59ef314c0fe79d1cd14597d7d6df4fb3 Mon Sep 17 00:00:00 2001 From: Konstantin Seurer Date: Mon, 21 Aug 2023 13:30:12 +0200 Subject: [PATCH] radv/rt: Insert rt_return_amd before lowering shader calls MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Also skips running nir_lower_shader_calls for the traversal shader. This will be used to skip the pass and the rt_return_amd insertion for monolithic raygen shaders. Reviewed-by: Daniel Schürmann Part-of: --- src/amd/vulkan/radv_pipeline_rt.c | 24 ++++++++++++++++-------- src/amd/vulkan/radv_rt_shader.c | 7 ------- 2 files changed, 16 insertions(+), 15 deletions(-) diff --git a/src/amd/vulkan/radv_pipeline_rt.c b/src/amd/vulkan/radv_pipeline_rt.c index fb9b35ec8c2..7b63f6b8cd3 100644 --- a/src/amd/vulkan/radv_pipeline_rt.c +++ b/src/amd/vulkan/radv_pipeline_rt.c @@ -22,6 +22,7 @@ */ #include "nir/nir.h" +#include "nir/nir_builder.h" #include "radv_debug.h" #include "radv_private.h" @@ -371,16 +372,23 @@ radv_rt_nir_to_asm(struct radv_device *device, struct vk_pipeline_cache *cache, */ NIR_PASS_V(stage->nir, move_rt_instructions); - const nir_lower_shader_calls_options opts = { - .address_format = nir_address_format_32bit_offset, - .stack_alignment = 16, - .localized_loads = true, - .vectorizer_callback = radv_mem_vectorize_callback, - .vectorizer_data = &device->physical_device->rad_info.gfx_level, - }; uint32_t num_resume_shaders = 0; nir_shader **resume_shaders = NULL; - nir_lower_shader_calls(stage->nir, &opts, &resume_shaders, &num_resume_shaders, stage->nir); + + if (stage->stage != MESA_SHADER_INTERSECTION) { + nir_builder b = nir_builder_at(nir_after_cf_list(&nir_shader_get_entrypoint(stage->nir)->body)); + nir_rt_return_amd(&b); + + const nir_lower_shader_calls_options opts = { + .address_format = nir_address_format_32bit_offset, + .stack_alignment = 16, + .localized_loads = true, + .vectorizer_callback = radv_mem_vectorize_callback, + .vectorizer_data = &device->physical_device->rad_info.gfx_level, + }; + nir_lower_shader_calls(stage->nir, &opts, &resume_shaders, &num_resume_shaders, stage->nir); + } + unsigned num_shaders = num_resume_shaders + 1; nir_shader **shaders = ralloc_array(stage->nir, nir_shader *, num_shaders); if (!shaders) diff --git a/src/amd/vulkan/radv_rt_shader.c b/src/amd/vulkan/radv_rt_shader.c index 2026ff98ac1..082ba47d32c 100644 --- a/src/amd/vulkan/radv_rt_shader.c +++ b/src/amd/vulkan/radv_rt_shader.c @@ -808,13 +808,6 @@ radv_parse_rt_stage(struct radv_device *device, const VkPipelineShaderStageCreat nir_shader *shader = radv_shader_spirv_to_nir(device, &rt_stage, key, false); - if (shader->info.stage == MESA_SHADER_RAYGEN || shader->info.stage == MESA_SHADER_CLOSEST_HIT || - shader->info.stage == MESA_SHADER_CALLABLE || shader->info.stage == MESA_SHADER_MISS) { - nir_block *last_block = nir_impl_last_block(nir_shader_get_entrypoint(shader)); - nir_builder b_inner = nir_builder_at(nir_after_block(last_block)); - nir_rt_return_amd(&b_inner); - } - NIR_PASS(_, shader, nir_split_struct_vars, nir_var_ray_hit_attrib); NIR_PASS(_, shader, nir_lower_indirect_derefs, nir_var_ray_hit_attrib, UINT32_MAX); NIR_PASS(_, shader, nir_split_array_vars, nir_var_ray_hit_attrib);