ac: update amdgpu_drm.h for uq metadata query info
struct drm_amdgpu_info_uq_fw_areas is renamed to drm_amdgpu_info_uq_metadata. query infor structure for compute and sdma is added. Reviewed-by: Marek Olšák <marek.olsak@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38647>
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@@ -1491,27 +1491,6 @@ struct drm_amdgpu_info_hw_ip {
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__u32 ip_discovery_version;
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};
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/* GFX metadata BO sizes and alignment info (in bytes) */
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struct drm_amdgpu_info_uq_fw_areas_gfx {
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/* shadow area size */
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__u32 shadow_size;
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/* shadow area base virtual mem alignment */
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__u32 shadow_alignment;
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/* context save area size */
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__u32 csa_size;
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/* context save area base virtual mem alignment */
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__u32 csa_alignment;
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};
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/* IP specific metadata related information used in the
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* subquery AMDGPU_INFO_UQ_FW_AREAS
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*/
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struct drm_amdgpu_info_uq_fw_areas {
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union {
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struct drm_amdgpu_info_uq_fw_areas_gfx gfx;
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};
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};
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struct drm_amdgpu_info_num_handles {
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/** Max handles as supported by firmware for UVD */
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__u32 uvd_max_handles;
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@@ -1575,6 +1554,39 @@ struct drm_amdgpu_info_gpuvm_fault {
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__u32 vmhub;
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};
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struct drm_amdgpu_info_uq_metadata_gfx {
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/* shadow area size for gfx11 */
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__u32 shadow_size;
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/* shadow area base virtual alignment for gfx11 */
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__u32 shadow_alignment;
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/* context save area size for gfx11 */
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__u32 csa_size;
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/* context save area base virtual alignment for gfx11 */
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__u32 csa_alignment;
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};
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struct drm_amdgpu_info_uq_metadata_compute {
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/* EOP size for gfx11 */
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__u32 eop_size;
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/* EOP base virtual alignment for gfx11 */
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__u32 eop_alignment;
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};
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struct drm_amdgpu_info_uq_metadata_sdma {
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/* context save area size for sdma6 */
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__u32 csa_size;
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/* context save area base virtual alignment for sdma6 */
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__u32 csa_alignment;
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};
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struct drm_amdgpu_info_uq_metadata {
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union {
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struct drm_amdgpu_info_uq_metadata_gfx gfx;
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struct drm_amdgpu_info_uq_metadata_compute compute;
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struct drm_amdgpu_info_uq_metadata_sdma sdma;
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};
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};
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/*
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* Supported GPU families
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*/
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