From f28d2c10409a395daad65600f9cb33e7a6172dac Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Roberto=20de=20Souza?= Date: Tue, 2 Jul 2024 08:51:45 -0700 Subject: [PATCH] intel/perf: Adjust EU count for Xe2+ MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Xe2+ OA equations expects actual EU count but KMD returns legacy EU count. Reviewed-by: Lionel Landwerlin Signed-off-by: José Roberto de Souza Part-of: --- src/intel/perf/intel_perf.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/src/intel/perf/intel_perf.c b/src/intel/perf/intel_perf.c index a50dbd6d06c..a20364954a7 100644 --- a/src/intel/perf/intel_perf.c +++ b/src/intel/perf/intel_perf.c @@ -342,6 +342,14 @@ compute_topology_builtins(struct intel_perf_config *perf) perf->sys_vars.n_eu_sub_slices = intel_device_info_subslice_total(devinfo); perf->sys_vars.n_eus = intel_device_info_eu_total(devinfo); + /* Xe2+ OA equations expects actual EU count but KMD returns legacy EU + * count. + */ + if (devinfo->verx10 >= 200) { + perf->sys_vars.n_eu_slice0123 /= 2; + perf->sys_vars.n_eus /= 2; + } + /* The subslice mask builtin contains bits for all slices. Prior to Gfx11 * it had groups of 3bits for each slice, on Gfx11 and above it's 8bits for * each slice.