From f2495f47a718e3c0cef739f2c8d2f8579bfc45fd Mon Sep 17 00:00:00 2001 From: M Henning Date: Fri, 20 Oct 2023 23:35:49 -0400 Subject: [PATCH] nvk: Use load_global_constant for ubo loads and support load_global_constant in nak Part-of: --- src/nouveau/compiler/nak_from_nir.rs | 10 ++++++++-- src/nouveau/compiler/nak_nir.c | 2 +- src/nouveau/vulkan/nvk_nir_lower_descriptors.c | 6 +++--- src/nouveau/vulkan/nvk_shader.c | 11 +++++------ 4 files changed, 17 insertions(+), 12 deletions(-) diff --git a/src/nouveau/compiler/nak_from_nir.rs b/src/nouveau/compiler/nak_from_nir.rs index d87542cc891..9b7d2cad1e3 100644 --- a/src/nouveau/compiler/nak_from_nir.rs +++ b/src/nouveau/compiler/nak_from_nir.rs @@ -1567,15 +1567,21 @@ impl<'a> ShaderFromNir<'a> { nir_intrinsic_load_barycentric_centroid => (), nir_intrinsic_load_barycentric_pixel => (), nir_intrinsic_load_barycentric_sample => (), - nir_intrinsic_load_global => { + nir_intrinsic_load_global | nir_intrinsic_load_global_constant => { let size_B = (intrin.def.bit_size() / 8) * intrin.def.num_components(); assert!(u32::from(size_B) <= intrin.align()); + let order = + if intrin.intrinsic == nir_intrinsic_load_global_constant { + MemOrder::Constant + } else { + MemOrder::Strong(MemScope::System) + }; let access = MemAccess { addr_type: MemAddrType::A64, mem_type: MemType::from_size(size_B, false), space: MemSpace::Global, - order: MemOrder::Strong(MemScope::System), + order: order, }; let (addr, offset) = self.get_io_addr_offset(&srcs[0], 32); let dst = b.alloc_ssa(RegFile::GPR, size_B.div_ceil(4)); diff --git a/src/nouveau/compiler/nak_nir.c b/src/nouveau/compiler/nak_nir.c index 8884a62f957..c791b9bf543 100644 --- a/src/nouveau/compiler/nak_nir.c +++ b/src/nouveau/compiler/nak_nir.c @@ -813,7 +813,7 @@ nak_postprocess_nir(nir_shader *nir, } nir_lower_mem_access_bit_sizes_options mem_bit_size_options = { - .modes = nir_var_mem_ubo | nir_var_mem_generic, + .modes = nir_var_mem_constant | nir_var_mem_ubo | nir_var_mem_generic, .callback = nak_mem_access_size_align, }; OPT(nir, nir_lower_mem_access_bit_sizes, &mem_bit_size_options); diff --git a/src/nouveau/vulkan/nvk_nir_lower_descriptors.c b/src/nouveau/vulkan/nvk_nir_lower_descriptors.c index 2a8e46368ff..cb313673d56 100644 --- a/src/nouveau/vulkan/nvk_nir_lower_descriptors.c +++ b/src/nouveau/vulkan/nvk_nir_lower_descriptors.c @@ -586,9 +586,9 @@ lower_load_ssbo_descriptor(nir_builder *b, nir_intrinsic_instr *intrin, case nir_address_format_64bit_global: /* Mask off the binding stride */ addr = nir_iand_imm(b, addr, BITFIELD64_MASK(56)); - desc = nir_build_load_global(b, 1, 64, addr, - .access = ACCESS_NON_WRITEABLE, - .align_mul = 16, .align_offset = 0); + desc = nir_build_load_global_constant(b, 1, 64, addr, + .align_mul = 16, + .align_offset = 0); break; case nir_address_format_64bit_global_32bit_offset: { diff --git a/src/nouveau/vulkan/nvk_shader.c b/src/nouveau/vulkan/nvk_shader.c index ec4b6f7ab7f..910e01a172a 100644 --- a/src/nouveau/vulkan/nvk_shader.c +++ b/src/nouveau/vulkan/nvk_shader.c @@ -239,12 +239,11 @@ lower_load_global_constant_offset_instr(nir_builder *b, } nir_def *val = - nir_build_load_global(b, intrin->def.num_components, - intrin->def.bit_size, - nir_iadd(b, base_addr, nir_u2u64(b, offset)), - .access = nir_intrinsic_access(intrin), - .align_mul = nir_intrinsic_align_mul(intrin), - .align_offset = nir_intrinsic_align_offset(intrin)); + nir_build_load_global_constant(b, intrin->def.num_components, + intrin->def.bit_size, + nir_iadd(b, base_addr, nir_u2u64(b, offset)), + .align_mul = nir_intrinsic_align_mul(intrin), + .align_offset = nir_intrinsic_align_offset(intrin)); if (intrin->intrinsic == nir_intrinsic_load_global_constant_bounded) { nir_pop_if(b, NULL);