From f232c404d3043d5c27029d63171dcaa0291efde4 Mon Sep 17 00:00:00 2001 From: Samuel Pitoiset Date: Wed, 7 Apr 2021 15:41:05 +0200 Subject: [PATCH] ac/surface: store the HTILE pitch to the surface MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This will be used to copy VRS rates to the HTILE buffer. Signed-off-by: Samuel Pitoiset Reviewed-by: Bas Nieuwenhuizen Reviewed-by: Marek Olšák Part-of: --- src/amd/common/ac_surface.c | 2 ++ src/amd/common/ac_surface.h | 1 + 2 files changed, 3 insertions(+) diff --git a/src/amd/common/ac_surface.c b/src/amd/common/ac_surface.c index e5a129bbb30..5ef3a0d7e84 100644 --- a/src/amd/common/ac_surface.c +++ b/src/amd/common/ac_surface.c @@ -742,6 +742,7 @@ static int gfx6_compute_level(ADDR_HANDLE addrlib, const struct ac_surf_config * surf->meta_size = AddrHtileOut->htileBytes; surf->meta_slice_size = AddrHtileOut->sliceSize; surf->meta_alignment_log2 = util_logbase2(AddrHtileOut->baseAlign); + surf->meta_pitch = AddrHtileOut->pitch; surf->num_meta_levels = level + 1; } } @@ -1668,6 +1669,7 @@ static int gfx9_compute_miptree(struct ac_addrlib *addrlib, const struct radeon_ surf->meta_size = hout.htileBytes; surf->meta_slice_size = hout.sliceSize; surf->meta_alignment_log2 = util_logbase2(hout.baseAlign); + surf->meta_pitch = hout.pitch; surf->num_meta_levels = in->numMipLevels; for (unsigned i = 0; i < in->numMipLevels; i++) { diff --git a/src/amd/common/ac_surface.h b/src/amd/common/ac_surface.h index 8674e9c9a72..b3207026d9f 100644 --- a/src/amd/common/ac_surface.h +++ b/src/amd/common/ac_surface.h @@ -360,6 +360,7 @@ struct radeon_surf { /* DCC and HTILE (they are very small) */ uint32_t meta_size; uint32_t meta_slice_size; + uint32_t meta_pitch; uint32_t cmask_size; uint32_t cmask_slice_size;