diff --git a/src/asahi/genxml/cmdbuf.xml b/src/asahi/genxml/cmdbuf.xml
index c497b791283..7591d04c99c 100644
--- a/src/asahi/genxml/cmdbuf.xml
+++ b/src/asahi/genxml/cmdbuf.xml
@@ -271,10 +271,10 @@
     -->
     <field name="Level offset (sw)" size="27" start="128" type="uint" modifier="shr(7)"/>
     <field name="Aligned width MSAA (sw)" size="15" start="128" type="uint"/>
+    <field name="Sample count log2 (sw)" size="2" start="143" type="uint"/>
     <field name="Tile width (sw)" size="3" start="155" type="uint" modifier="log2"/>
     <field name="Tile height (sw)" size="3" start="158" type="uint" modifier="log2"/>
     <field name="Layer stride (sw)" size="27" start="161" type="uint" modifier="shr(7)"/>
-    <field name="Sample count log2 (sw)" size="2" start="188" type="uint"/>
     <field name="Buffer offset (sw)" size="32" start="128" type="uint"/>
   </struct>
 
diff --git a/src/asahi/vulkan/hk_image_view.c b/src/asahi/vulkan/hk_image_view.c
index 572c3bae238..7b44a94c8c0 100644
--- a/src/asahi/vulkan/hk_image_view.c
+++ b/src/asahi/vulkan/hk_image_view.c
@@ -501,12 +501,12 @@ pack_pbe(struct hk_device *dev, struct hk_image_view *view, unsigned view_plane,
             cfg.aligned_width_msaa_sw =
                align(u_minify(layout->width_px, level),
                      layout->tilesize_el[level].width_el);
+
+            cfg.sample_count_log2_sw = util_logbase2(image->vk.samples);
          } else {
             cfg.level_offset_sw = ail_get_level_offset_B(layout, cfg.level);
          }
 
-         cfg.sample_count_log2_sw = util_logbase2(image->vk.samples);
-
          if (layout->tiling != AIL_TILING_LINEAR) {
             struct ail_tile tile_size = layout->tilesize_el[level];
             cfg.tile_width_sw = tile_size.width_el;
diff --git a/src/gallium/drivers/asahi/agx_state.c b/src/gallium/drivers/asahi/agx_state.c
index 158e8b60202..a9e5e4bbc1f 100644
--- a/src/gallium/drivers/asahi/agx_state.c
+++ b/src/gallium/drivers/asahi/agx_state.c
@@ -1303,13 +1303,13 @@ agx_batch_upload_pbe(struct agx_batch *batch, struct agx_pbe_packed *out,
             cfg.aligned_width_msaa_sw =
                align(u_minify(view->resource->width0, level),
                      tex->layout.tilesize_el[level].width_el);
+
+            cfg.sample_count_log2_sw = util_logbase2(tex->base.nr_samples);
          } else {
             cfg.level_offset_sw =
                ail_get_level_offset_B(&tex->layout, cfg.level);
          }
 
-         cfg.sample_count_log2_sw = util_logbase2(tex->base.nr_samples);
-
          if (tex->layout.tiling == AIL_TILING_GPU || emrt) {
             struct ail_tile tile_size = tex->layout.tilesize_el[level];
             cfg.tile_width_sw = tile_size.width_el;