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i965: make GT3 machines work as GT3 instead of GT2

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We were not allowed to say the "GT3" name, but we really needed to
have the PCI IDs because too many people had such machines, so we had
to make the GT3 machines work as GT2.

Let's just say that GT2_PLUS was a short for GT2_PLUS_1 :)

NOTE: This is a candidate for stable branches.

Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
This commit is contained in:
Paulo Zanoni
2012-08-10 12:06:37 -03:00
committed by Kenneth Graunke
parent d0b82b1add
commit f1d2b37317
3 changed files with 53 additions and 49 deletions
Download Patch File Download Diff File Expand all files Collapse all files
include/pci_ids/i965_pci_ids.h
+12 -12
View File
@@ -28,40 +28,40 @@ CHIPSET(0x015a, IVYBRIDGE_S_GT1, ivb_gt1)
CHIPSET(0x016a, IVYBRIDGE_S_GT2, ivb_gt2)
CHIPSET(0x0402, HASWELL_GT1, hsw_gt1)
CHIPSET(0x0412, HASWELL_GT2, hsw_gt2)
CHIPSET(0x0422, HASWELL_GT2_PLUS, hsw_gt2)
CHIPSET(0x0422, HASWELL_GT3, hsw_gt3)
CHIPSET(0x0406, HASWELL_M_GT1, hsw_gt1)
CHIPSET(0x0416, HASWELL_M_GT2, hsw_gt2)
CHIPSET(0x0426, HASWELL_M_GT2_PLUS, hsw_gt2)
CHIPSET(0x0426, HASWELL_M_GT3, hsw_gt3)
CHIPSET(0x040A, HASWELL_S_GT1, hsw_gt1)
CHIPSET(0x041A, HASWELL_S_GT2, hsw_gt2)
CHIPSET(0x042A, HASWELL_S_GT2_PLUS, hsw_gt2)
CHIPSET(0x042A, HASWELL_S_GT3, hsw_gt3)
CHIPSET(0x0C02, HASWELL_SDV_GT1, hsw_gt1)
CHIPSET(0x0C12, HASWELL_SDV_GT2, hsw_gt2)
CHIPSET(0x0C22, HASWELL_SDV_GT2_PLUS, hsw_gt2)
CHIPSET(0x0C22, HASWELL_SDV_GT3, hsw_gt3)
CHIPSET(0x0C06, HASWELL_SDV_M_GT1, hsw_gt1)
CHIPSET(0x0C16, HASWELL_SDV_M_GT2, hsw_gt2)
CHIPSET(0x0C26, HASWELL_SDV_M_GT2_PLUS, hsw_gt2)
CHIPSET(0x0C26, HASWELL_SDV_M_GT3, hsw_gt3)
CHIPSET(0x0C0A, HASWELL_SDV_S_GT1, hsw_gt1)
CHIPSET(0x0C1A, HASWELL_SDV_S_GT2, hsw_gt2)
CHIPSET(0x0C2A, HASWELL_SDV_S_GT2_PLUS, hsw_gt2)
CHIPSET(0x0C2A, HASWELL_SDV_S_GT3, hsw_gt3)
CHIPSET(0x0A02, HASWELL_ULT_GT1, hsw_gt1)
CHIPSET(0x0A12, HASWELL_ULT_GT2, hsw_gt2)
CHIPSET(0x0A22, HASWELL_ULT_GT2_PLUS, hsw_gt2)
CHIPSET(0x0A22, HASWELL_ULT_GT3, hsw_gt3)
CHIPSET(0x0A06, HASWELL_ULT_M_GT1, hsw_gt1)
CHIPSET(0x0A16, HASWELL_ULT_M_GT2, hsw_gt2)
CHIPSET(0x0A26, HASWELL_ULT_M_GT2_PLUS, hsw_gt2)
CHIPSET(0x0A26, HASWELL_ULT_M_GT3, hsw_gt3)
CHIPSET(0x0A0A, HASWELL_ULT_S_GT1, hsw_gt1)
CHIPSET(0x0A1A, HASWELL_ULT_S_GT2, hsw_gt2)
CHIPSET(0x0A2A, HASWELL_ULT_S_GT2_PLUS, hsw_gt2)
CHIPSET(0x0A2A, HASWELL_ULT_S_GT3, hsw_gt3)
CHIPSET(0x0D02, HASWELL_CRW_GT1, hsw_gt1)
CHIPSET(0x0D12, HASWELL_CRW_GT2, hsw_gt2)
CHIPSET(0x0D22, HASWELL_CRW_GT2_PLUS, hsw_gt2)
CHIPSET(0x0D22, HASWELL_CRW_GT3, hsw_gt3)
CHIPSET(0x0D06, HASWELL_CRW_M_GT1, hsw_gt1)
CHIPSET(0x0D16, HASWELL_CRW_M_GT2, hsw_gt2)
CHIPSET(0x0D26, HASWELL_CRW_M_GT2_PLUS, hsw_gt2)
CHIPSET(0x0D26, HASWELL_CRW_M_GT3, hsw_gt3)
CHIPSET(0x0D0A, HASWELL_CRW_S_GT1, hsw_gt1)
CHIPSET(0x0D1A, HASWELL_CRW_S_GT2, hsw_gt2)
CHIPSET(0x0D2A, HASWELL_CRW_S_GT2_PLUS, hsw_gt2)
CHIPSET(0x0D2A, HASWELL_CRW_S_GT3, hsw_gt3)
CHIPSET(0x0F31, BAYTRAIL_M_1, byt)
CHIPSET(0x0F32, BAYTRAIL_M_2, byt)
CHIPSET(0x0F33, BAYTRAIL_M_3, byt)