From f19c5f4fcc195b63b20528d27521f88dc3d48a04 Mon Sep 17 00:00:00 2001 From: Lionel Landwerlin Date: Mon, 2 Dec 2024 15:00:07 +0200 Subject: [PATCH] brw: use meaningful io locations for system values Signed-off-by: Lionel Landwerlin Reviewed-by: Caio Oliveira Part-of: --- src/intel/compiler/brw_compiler.h | 8 ++++++++ src/intel/compiler/brw_nir.c | 6 +++--- 2 files changed, 11 insertions(+), 3 deletions(-) diff --git a/src/intel/compiler/brw_compiler.h b/src/intel/compiler/brw_compiler.h index 21185d92ae5..dcbec3ee3c0 100644 --- a/src/intel/compiler/brw_compiler.h +++ b/src/intel/compiler/brw_compiler.h @@ -230,6 +230,14 @@ struct brw_base_prog_key { #define MAX_VK_VERT_ATTRIB (VERT_ATTRIB_GENERIC0 + 29) #define MAX_HW_VERT_ATTRIB (VERT_ATTRIB_GENERIC0 + 34) +/** + * Use the last 2 slots : + * - slot 32: start vertex, vertex count, instance count, start instance + * - slot 33: base vertex, base instance, draw id + */ +#define BRW_SVGS_VE_INDEX (32) +#define BRW_DRAWID_VE_INDEX (33) + /** The program key for Vertex Shaders. */ struct brw_vs_prog_key { struct brw_base_prog_key base; diff --git a/src/intel/compiler/brw_nir.c b/src/intel/compiler/brw_nir.c index db21c7c16b0..77650e8ccc0 100644 --- a/src/intel/compiler/brw_nir.c +++ b/src/intel/compiler/brw_nir.c @@ -464,6 +464,7 @@ brw_nir_lower_vs_inputs(nir_shader *nir) load->src[0] = nir_src_for_ssa(nir_imm_int(&b, 0)); unsigned input_offset = 0; + unsigned location = BRW_SVGS_VE_INDEX; switch (intrin->intrinsic) { case nir_intrinsic_load_first_vertex: nir_intrinsic_set_component(load, 0); @@ -483,6 +484,7 @@ brw_nir_lower_vs_inputs(nir_shader *nir) * gl_VertexID and friends if any of them exist. */ input_offset += has_sgvs ? 1 : 0; + location = BRW_DRAWID_VE_INDEX; if (intrin->intrinsic == nir_intrinsic_load_draw_id) nir_intrinsic_set_component(load, 0); else @@ -498,7 +500,7 @@ brw_nir_lower_vs_inputs(nir_shader *nir) */ nir_intrinsic_set_base(load, num_inputs + input_offset); struct nir_io_semantics io = { - .location = util_last_bit64(nir->info.inputs_read) + input_offset, + .location = VERT_ATTRIB_GENERIC0 + location, .num_slots = 1, }; nir_intrinsic_set_io_semantics(load, io); @@ -2484,5 +2486,3 @@ brw_nir_lower_simd(nir_shader *nir, unsigned dispatch_width) return nir_shader_lower_instructions(nir, filter_simd, lower_simd, (void *)(uintptr_t)dispatch_width); } - -