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nir,aco: optimize FP16_OFVL pattern created by vkd3d-proton

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Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35434>
This commit is contained in:
Georg Lehmann
2025-06-10 15:10:02 +02:00
committed by Marge Bot
parent 9e6adcbca0
commit f047a67fba
6 changed files with 34 additions and 1 deletions
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src/amd/common/nir/ac_nir.c
+1
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@@ -88,6 +88,7 @@ void ac_nir_set_options(struct radeon_info *info, bool use_llvm,
options->has_msad = true;
options->has_shfr32 = true;
options->has_mul24_relaxed = true;
options->has_f2e4m3fn_satfn = !use_llvm && info->gfx_level >= GFX12;
options->lower_int64_options = nir_lower_imul64 | nir_lower_imul_high64 | nir_lower_imul_2x32_64 | nir_lower_divmod64 |
nir_lower_minmax64 | nir_lower_iabs64 | nir_lower_iadd_sat64 | nir_lower_conv64 |
nir_lower_bitfield_extract64;
src/amd/compiler/instruction_selection/aco_isel_setup.cpp
+1
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@@ -417,6 +417,7 @@ init_context(isel_context* ctx, nir_shader* shader)
break;
case nir_op_f2e4m3fn:
case nir_op_f2e4m3fn_sat:
case nir_op_f2e4m3fn_satfn:
case nir_op_f2e5m2:
case nir_op_f2e5m2_sat:
case nir_op_fmulz:
src/amd/compiler/instruction_selection/aco_select_nir_alu.cpp
+3 -1
View File
@@ -2555,6 +2555,7 @@ visit_alu_instr(isel_context* ctx, nir_alu_instr* instr)
}
case nir_op_f2e4m3fn:
case nir_op_f2e4m3fn_sat:
case nir_op_f2e4m3fn_satfn:
case nir_op_f2e5m2:
case nir_op_f2e5m2_sat: {
Operand src[2];
@@ -2588,7 +2589,8 @@ visit_alu_instr(isel_context* ctx, nir_alu_instr* instr)
aco_opcode opcode = instr->op == nir_op_f2e4m3fn || instr->op == nir_op_f2e4m3fn_sat
? aco_opcode::v_cvt_pk_fp8_f32
: aco_opcode::v_cvt_pk_bf8_f32;
: instr->op == nir_op_f2e4m3fn_satfn ? aco_opcode::p_v_cvt_pk_fp8_f32_ovfl
: aco_opcode::v_cvt_pk_bf8_f32;
bld.vop3(opcode, Definition(dst), src[0], src[1]);
if (instr->def.num_components == 2)
emit_split_vector(ctx, dst, 2);