From ef12565a378848ad9a65621ea01d66c1719859cf Mon Sep 17 00:00:00 2001 From: Francisco Jerez Date: Mon, 12 Sep 2022 16:47:19 -0700 Subject: [PATCH] intel/fs: Map all VS input attributes to ATTR register number 0. Instead of treating fs_reg::nr as an offset for ATTR registers simply consider different indices as denoting disjoint spaces that can never be accessed simultaneously by a single region. From now on geometry stages will just use ATTR #0 for everything and select specific attributes via offset() with the native dispatch width of the program, which should work on current platforms as well as on Xe2+. See "intel/fs: Map all GS input attributes to ATTR register number 0." for the rationale. Reviewed-by: Caio Oliveira Part-of: --- src/intel/compiler/brw_fs_nir.cpp | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/src/intel/compiler/brw_fs_nir.cpp b/src/intel/compiler/brw_fs_nir.cpp index dca97f3e798..9215b89ab6f 100644 --- a/src/intel/compiler/brw_fs_nir.cpp +++ b/src/intel/compiler/brw_fs_nir.cpp @@ -2652,9 +2652,10 @@ fs_nir_emit_vs_intrinsic(nir_to_brw_state &ntb, case nir_intrinsic_load_input: { assert(instr->def.bit_size == 32); - fs_reg src = fs_reg(ATTR, nir_intrinsic_base(instr) * 4, dest.type); - src = offset(src, bld, nir_intrinsic_component(instr)); - src = offset(src, bld, nir_src_as_uint(instr->src[0])); + const fs_reg src = offset(fs_reg(ATTR, 0, dest.type), bld, + nir_intrinsic_base(instr) * 4 + + nir_intrinsic_component(instr) + + nir_src_as_uint(instr->src[0])); for (unsigned i = 0; i < instr->num_components; i++) bld.MOV(offset(dest, bld, i), offset(src, bld, i));