AlexIndustrial/mesa
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

r600/sb: give the scheduler more margin to find valid instructions groups

Browse Source 
For instruction sequences that change the address register with every load
the current limit to bail out of the scheduler and reject the optimisation
was too tight, i.e. it was expected that at least one pending instruction
would be scheduled each time.

Give the scheduler more margin to sort out these load sequences by allowing
a number of rounds where no instruction is scheduled.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106163

Signed-off-by: Gert Wollny <gw.fossdev@gmail.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
This commit is contained in:
Gert Wollny
2018-06-01 01:20:54 +02:00
committed by Dave Airlie
parent cd7db0ab0a
commit eebb65258d
1 changed files with 10 additions and 3 deletions
Download Patch File Download Diff File Expand all files Collapse all files
src/gallium/drivers/r600/sb/sb_sched.cpp
+10 -3
View File
@@ -1154,14 +1154,21 @@ bool post_scheduler::schedule_alu(container_node *c) {
assert(!ready.empty() || !ready_copies.empty());
bool improving = true;
/* This number is rather arbitrary, important is that the scheduler has
* more than one try to create an instruction group
*/
int improving = 10;
int last_pending = pending.count();
while (improving) {
while (improving > 0) {
prev_regmap = regmap;
if (!prepare_alu_group()) {
int new_pending = pending.count();
improving = (new_pending < last_pending) || (last_pending == 0);
if ((new_pending < last_pending) || (last_pending == 0))
improving = 10;
else
--improving;
last_pending = new_pending;
if (alu.current_idx[0] || alu.current_idx[1]) {