From ee77dde39684686b4bda2e031894848c27ba3374 Mon Sep 17 00:00:00 2001 From: Samuel Pitoiset Date: Fri, 9 Apr 2021 13:58:53 +0200 Subject: [PATCH] radv: configure the VRS combiners when an attachment is used Signed-off-by: Samuel Pitoiset Reviewed-by: Bas Nieuwenhuizen Part-of: --- src/amd/vulkan/radv_cmd_buffer.c | 38 +++++++++++++++++++++++++++++++- src/amd/vulkan/radv_pipeline.c | 5 ++--- 2 files changed, 39 insertions(+), 4 deletions(-) diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c index e7d44824231..a463e5cc18a 100644 --- a/src/amd/vulkan/radv_cmd_buffer.c +++ b/src/amd/vulkan/radv_cmd_buffer.c @@ -1523,10 +1523,41 @@ static void radv_emit_fragment_shading_rate(struct radv_cmd_buffer *cmd_buffer) { struct radv_pipeline *pipeline = cmd_buffer->state.pipeline; + const struct radv_subpass *subpass = cmd_buffer->state.subpass; struct radv_dynamic_state *d = &cmd_buffer->state.dynamic; uint32_t rate_x = MIN2(2, d->fragment_shading_rate.size.width) - 1; uint32_t rate_y = MIN2(2, d->fragment_shading_rate.size.height) - 1; uint32_t pa_cl_vrs_cntl = pipeline->graphics.vrs.pa_cl_vrs_cntl; + uint32_t vertex_comb_mode = d->fragment_shading_rate.combiner_ops[0]; + uint32_t htile_comb_mode = d->fragment_shading_rate.combiner_ops[1]; + + if (subpass && !subpass->vrs_attachment) { + /* When the current subpass has no VRS attachment, the VRS rates are expected to be 1x1, so we + * can cheat by tweaking the different combiner modes. + */ + switch (htile_comb_mode) { + case VK_FRAGMENT_SHADING_RATE_COMBINER_OP_MIN_KHR: + /* The result of min(A, 1x1) is always 1x1. */ + FALLTHROUGH; + case VK_FRAGMENT_SHADING_RATE_COMBINER_OP_REPLACE_KHR: + /* Force the per-draw VRS rate to 1x1. */ + rate_x = rate_y = 0; + + /* As the result of min(A, 1x1) or replace(A, 1x1) are always 1x1, set the vertex rate + * combiner mode as passthrough. + */ + vertex_comb_mode = V_028848_VRS_COMB_MODE_PASSTHRU; + break; + case VK_FRAGMENT_SHADING_RATE_COMBINER_OP_MAX_KHR: + /* The result of max(A, 1x1) is always A. */ + FALLTHROUGH; + case VK_FRAGMENT_SHADING_RATE_COMBINER_OP_KEEP_KHR: + /* Nothing to do here because the SAMPLE_ITER combiner mode should already be passthrough. */ + break; + default: + break; + } + } /* Emit per-draw VRS rate which is the first combiner. */ radeon_set_uconfig_reg(cmd_buffer->cs, R_03098C_GE_VRS_RATE, @@ -1535,7 +1566,12 @@ radv_emit_fragment_shading_rate(struct radv_cmd_buffer *cmd_buffer) /* VERTEX_RATE_COMBINER_MODE controls the combiner mode between the * draw rate and the vertex rate. */ - pa_cl_vrs_cntl |= S_028848_VERTEX_RATE_COMBINER_MODE(d->fragment_shading_rate.combiner_ops[0]); + pa_cl_vrs_cntl |= S_028848_VERTEX_RATE_COMBINER_MODE(vertex_comb_mode); + + /* HTILE_RATE_COMBINER_MODE controls the combiner mode between the primitive rate and the HTILE + * rate. + */ + pa_cl_vrs_cntl |= S_028848_HTILE_RATE_COMBINER_MODE(htile_comb_mode); radeon_set_context_reg(cmd_buffer->cs, R_028848_PA_CL_VRS_CNTL, pa_cl_vrs_cntl); } diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c index 2ea36b6c063..dab428497c4 100644 --- a/src/amd/vulkan/radv_pipeline.c +++ b/src/amd/vulkan/radv_pipeline.c @@ -1236,9 +1236,8 @@ gfx103_pipeline_init_vrs_state(struct radv_pipeline *pipeline, vrs->pa_cl_vrs_cntl = S_028848_SAMPLE_ITER_COMBINER_MODE(V_028848_VRS_COMB_MODE_PASSTHRU); } - /* Primitive and HTILE combiners are always passthrough. */ - vrs->pa_cl_vrs_cntl |= S_028848_PRIMITIVE_RATE_COMBINER_MODE(V_028848_VRS_COMB_MODE_PASSTHRU) | - S_028848_HTILE_RATE_COMBINER_MODE(V_028848_VRS_COMB_MODE_PASSTHRU); + /* The primitive combiner is always passthrough. */ + vrs->pa_cl_vrs_cntl |= S_028848_PRIMITIVE_RATE_COMBINER_MODE(V_028848_VRS_COMB_MODE_PASSTHRU); } static bool