diff --git a/src/amd/compiler/README-ISA.md b/src/amd/compiler/README-ISA.md
index 62f38dd849f..3bd7dfeb873 100644
--- a/src/amd/compiler/README-ISA.md
+++ b/src/amd/compiler/README-ISA.md
@@ -375,4 +375,5 @@ Triggered by:
 SALU writing then reading a SGPR that was previously used as a lane mask for a VALU.
 
 Mitigated by:
-A VALU instruction reading a SGPR or with literal, or a sa_sdst=0 wait: `s_waitcnt_depctr 0xfffe`
+A VALU instruction reading a non-exec SGPR before the SALU write, or a sa_sdst=0 wait:
+`s_waitcnt_depctr 0xfffe`
diff --git a/src/amd/compiler/aco_insert_NOPs.cpp b/src/amd/compiler/aco_insert_NOPs.cpp
index d6044e138f5..b9744434fd5 100644
--- a/src/amd/compiler/aco_insert_NOPs.cpp
+++ b/src/amd/compiler/aco_insert_NOPs.cpp
@@ -1485,7 +1485,8 @@ handle_instruction_gfx11(State& state, NOP_ctx_gfx11& ctx, aco_ptr<Instruction>&
 
          if (state.program->wave_size == 64) {
             for (Operand& op : instr->operands) {
-               if (op.isLiteral() || (!op.isConstant() && op.physReg().reg() < 128))
+               /* This should ignore exec reads */
+               if (!op.isConstant() && op.physReg().reg() < 126)
                   ctx.sgpr_read_by_valu_as_lanemask.reset();
             }
             switch (instr->opcode) {