diff --git a/src/amd/vpelib/meson.build b/src/amd/vpelib/meson.build index fdd4c598d58..9d7c3cd4850 100644 --- a/src/amd/vpelib/meson.build +++ b/src/amd/vpelib/meson.build @@ -86,6 +86,7 @@ vpe_files = files( 'src/chip/vpe10/inc/vpe10_command.h', 'src/chip/vpe10/inc/vpe10_plane_desc_writer.h', 'src/chip/vpe10/inc/vpe10_vpe_desc_writer.h', + 'src/chip/vpe10/inc/vpe10_config_writer.h', 'src/chip/vpe10/inc/vpe10_background.h', 'src/chip/vpe10/inc/vpe10_cm_common.h', 'src/chip/vpe10/inc/vpe10_vpec.h', @@ -112,12 +113,14 @@ vpe_files = files( 'src/chip/vpe10/vpe10_background.c', 'src/chip/vpe10/vpe10_cdc.c', 'src/chip/vpe10/vpe10_vpec.c', + 'src/chip/vpe10/vpe10_config_writer.c', + 'src/chip/vpe11/inc/vpe11_command.h', 'src/chip/vpe11/inc/vpe11_cmd_builder.h', 'src/chip/vpe11/inc/vpe11_resource.h', 'src/chip/vpe11/inc/vpe11_vpe_desc_writer.h', 'src/chip/vpe11/vpe11_cmd_builder.c', 'src/chip/vpe11/vpe11_resource.c', - 'src/chip/vpe11/vpe11_vpe_desc_writer.c', + 'src/chip/vpe11/vpe11_vpe_desc_writer.c' ) inc_amd_vpe = include_directories( diff --git a/src/amd/vpelib/src/chip/vpe10/inc/vpe10_cdc.h b/src/amd/vpelib/src/chip/vpe10/inc/vpe10_cdc.h index 710c5e93235..4f4aeedbd84 100644 --- a/src/amd/vpelib/src/chip/vpe10/inc/vpe10_cdc.h +++ b/src/amd/vpelib/src/chip/vpe10/inc/vpe10_cdc.h @@ -190,7 +190,8 @@ void vpe10_cdc_program_crossbar_config(struct cdc *cdc, enum vpe_surface_pixel_f void vpe10_cdc_program_global_sync( struct cdc *cdc, uint32_t vupdate_offset, uint32_t vupdate_width, uint32_t vready_offset); -void vpe10_cdc_program_p2b_config(struct cdc *cdc, enum vpe_surface_pixel_format format); +void vpe10_cdc_program_p2b_config(struct cdc *cdc, enum vpe_surface_pixel_format format, + enum vpe_swizzle_mode_values swizzle, const struct vpe_rect *viewport); /***** segment register programming *****/ void vpe10_cdc_program_viewport( diff --git a/src/amd/vpelib/src/chip/vpe10/inc/vpe10_config_writer.h b/src/amd/vpelib/src/chip/vpe10/inc/vpe10_config_writer.h new file mode 100644 index 00000000000..be1a9a695a1 --- /dev/null +++ b/src/amd/vpelib/src/chip/vpe10/inc/vpe10_config_writer.h @@ -0,0 +1,3 @@ +#include "config_writer.h" + +void vpe10_config_writer_init(struct config_writer *writer); diff --git a/src/amd/vpelib/src/chip/vpe10/inc/vpe10_mpc.h b/src/amd/vpelib/src/chip/vpe10/inc/vpe10_mpc.h index d0ac279e8e2..74c8284d799 100644 --- a/src/amd/vpelib/src/chip/vpe10/inc/vpe10_mpc.h +++ b/src/amd/vpelib/src/chip/vpe10/inc/vpe10_mpc.h @@ -795,19 +795,19 @@ extern "C" { reg_id_val VPMPC_BYPASS_BG_GB; \ reg_id_val VPMPC_HOST_READ_CONTROL; \ reg_id_val VPMPC_PENDING_STATUS_MISC; \ - reg_id_val VPMPC_OUT_MUX; \ - reg_id_val VPMPC_OUT_FLOAT_CONTROL; \ - reg_id_val VPMPC_OUT_DENORM_CONTROL; \ - reg_id_val VPMPC_OUT_DENORM_CLAMP_G_Y; \ - reg_id_val VPMPC_OUT_DENORM_CLAMP_B_CB; \ + reg_id_val VPMPC_OUT_MUX; \ + reg_id_val VPMPC_OUT_FLOAT_CONTROL; \ + reg_id_val VPMPC_OUT_DENORM_CONTROL; \ + reg_id_val VPMPC_OUT_DENORM_CLAMP_G_Y; \ + reg_id_val VPMPC_OUT_DENORM_CLAMP_B_CB; \ reg_id_val VPMPC_OUT_CSC_COEF_FORMAT; \ - reg_id_val VPMPC_OUT_CSC_MODE; \ - reg_id_val VPMPC_OUT_CSC_C11_C12_A; \ - reg_id_val VPMPC_OUT_CSC_C13_C14_A; \ - reg_id_val VPMPC_OUT_CSC_C21_C22_A; \ - reg_id_val VPMPC_OUT_CSC_C23_C24_A; \ - reg_id_val VPMPC_OUT_CSC_C31_C32_A; \ - reg_id_val VPMPC_OUT_CSC_C33_C34_A; \ + reg_id_val VPMPC_OUT_CSC_MODE; \ + reg_id_val VPMPC_OUT_CSC_C11_C12_A; \ + reg_id_val VPMPC_OUT_CSC_C13_C14_A; \ + reg_id_val VPMPC_OUT_CSC_C21_C22_A; \ + reg_id_val VPMPC_OUT_CSC_C23_C24_A; \ + reg_id_val VPMPC_OUT_CSC_C31_C32_A; \ + reg_id_val VPMPC_OUT_CSC_C33_C34_A; \ reg_id_val VPMPCC_TOP_SEL; \ reg_id_val VPMPCC_BOT_SEL; \ reg_id_val VPMPCC_VPOPP_ID; \ @@ -907,6 +907,7 @@ extern "C" { reg_id_val VPMPCC_MCM_1DLUT_RAMA_REGION_28_29; \ reg_id_val VPMPCC_MCM_1DLUT_RAMA_REGION_30_31; \ reg_id_val VPMPCC_MCM_1DLUT_RAMA_REGION_32_33; \ + reg_id_val VPMPCC_MCM_MEM_PWR_CTRL; #define MPC_REG_VARIABLE_LIST_VPE10 \ MPC_REG_VARIABLE_LIST_VPE10_COMMON \ @@ -951,7 +952,6 @@ extern "C" { reg_id_val VPMPCC_MCM_3DLUT_OUT_OFFSET_R; \ reg_id_val VPMPCC_MCM_3DLUT_OUT_OFFSET_G; \ reg_id_val VPMPCC_MCM_3DLUT_OUT_OFFSET_B; \ - reg_id_val VPMPCC_MCM_MEM_PWR_CTRL; #define MPC_FIELD_VARIABLE_LIST_VPE10_COMMON(type) \ diff --git a/src/amd/vpelib/src/chip/vpe10/vpe10_cdc.c b/src/amd/vpelib/src/chip/vpe10/vpe10_cdc.c index 4c79b68a6fa..18d473974cc 100644 --- a/src/amd/vpelib/src/chip/vpe10/vpe10_cdc.c +++ b/src/amd/vpelib/src/chip/vpe10/vpe10_cdc.c @@ -220,7 +220,8 @@ void vpe10_cdc_program_global_sync( BE0_VUPDATE_WIDTH, vupdate_width, BE0_VREADY_OFFSET, vready_offset); } -void vpe10_cdc_program_p2b_config(struct cdc *cdc, enum vpe_surface_pixel_format format) +void vpe10_cdc_program_p2b_config(struct cdc *cdc, enum vpe_surface_pixel_format format, + enum vpe_swizzle_mode_values swizzle, const struct vpe_rect *viewport) { uint32_t bar_sel0 = (uint32_t)MUX_SEL_CB_B; uint32_t bar_sel1 = (uint32_t)MUX_SEL_Y_G; diff --git a/src/amd/vpelib/src/chip/vpe10/vpe10_config_writer.c b/src/amd/vpelib/src/chip/vpe10/vpe10_config_writer.c new file mode 100644 index 00000000000..e4f586f57cd --- /dev/null +++ b/src/amd/vpelib/src/chip/vpe10/vpe10_config_writer.c @@ -0,0 +1,6 @@ +#include "vpe10_config_writer.h" + +void vpe10_config_writer_init(struct config_writer *writer) +{ + writer->gpu_addr_alignment = 0x2; +} diff --git a/src/amd/vpelib/src/chip/vpe10/vpe10_resource.c b/src/amd/vpelib/src/chip/vpe10/vpe10_resource.c index a2ee419a159..95c3dac8904 100644 --- a/src/amd/vpelib/src/chip/vpe10/vpe10_resource.c +++ b/src/amd/vpelib/src/chip/vpe10/vpe10_resource.c @@ -36,6 +36,7 @@ #include "vpe10_background.h" #include "vpe10_vpe_desc_writer.h" #include "vpe10_plane_desc_writer.h" +#include "vpe10_config_writer.h" #include "vpe10/inc/asic/bringup_vpe_6_1_0_offset.h" #include "vpe10/inc/asic/bringup_vpe_6_1_0_sh_mask.h" #include "vpe10/inc/asic/bringup_vpe_6_1_0_default.h" @@ -366,6 +367,7 @@ enum vpe_status vpe10_construct_resource(struct vpe_priv *vpe_priv, struct resou vpe10_construct_cmd_builder(vpe_priv, &res->cmd_builder); vpe10_construct_vpe_desc_writer(&vpe_priv->vpe_desc_writer); vpe10_construct_plane_desc_writer(&vpe_priv->plane_desc_writer); + vpe10_config_writer_init(&vpe_priv->config_writer); vpe_priv->num_pipe = 1; @@ -821,7 +823,8 @@ int32_t vpe10_program_backend( /* start back-end programming that can be shared among segments */ vpe_priv->be_cb_ctx.share = true; - cdc->funcs->program_p2b_config(cdc, surface_info->format); + cdc->funcs->program_p2b_config( + cdc, surface_info->format, surface_info->swizzle, &output_ctx->target_rect); cdc->funcs->program_global_sync(cdc, VPE10_CDC_VUPDATE_OFFSET_DEFAULT, VPE10_CDC_VUPDATE_WIDTH_DEFAULT, VPE10_CDC_VREADY_OFFSET_DEFAULT); diff --git a/src/amd/vpelib/src/chip/vpe11/vpe11_resource.c b/src/amd/vpelib/src/chip/vpe11/vpe11_resource.c index f618da66822..e10d663533f 100644 --- a/src/amd/vpelib/src/chip/vpe11/vpe11_resource.c +++ b/src/amd/vpelib/src/chip/vpe11/vpe11_resource.c @@ -37,6 +37,7 @@ #include "vpe10_background.h" #include "vpe10_plane_desc_writer.h" #include "vpe11_vpe_desc_writer.h" +#include "vpe10_config_writer.h" #include "vpe10/inc/asic/bringup_vpe_6_1_0_offset.h" #include "vpe10/inc/asic/bringup_vpe_6_1_0_sh_mask.h" #include "vpe10/inc/asic/bringup_vpe_6_1_0_default.h" @@ -173,6 +174,7 @@ enum vpe_status vpe11_construct_resource(struct vpe_priv *vpe_priv, struct resou vpe11_construct_cmd_builder(vpe_priv, &res->cmd_builder); vpe10_construct_plane_desc_writer(&vpe_priv->plane_desc_writer); vpe11_construct_vpe_desc_writer(&vpe_priv->vpe_desc_writer); + vpe10_config_writer_init(&vpe_priv->config_writer); vpe_priv->num_pipe = 1; diff --git a/src/amd/vpelib/src/core/config_writer.c b/src/amd/vpelib/src/core/config_writer.c index cd10df2b2e3..048dd9c230b 100644 --- a/src/amd/vpelib/src/core/config_writer.c +++ b/src/amd/vpelib/src/core/config_writer.c @@ -55,6 +55,18 @@ static inline void config_writer_new(struct config_writer *writer) if (writer->status != VPE_STATUS_OK) return; + uint16_t alignment = writer->gpu_addr_alignment; + uint64_t aligned_gpu_address = (writer->buf->gpu_va + alignment) & ~alignment; + uint64_t alignment_offset = aligned_gpu_address - writer->buf->gpu_va; + writer->buf->gpu_va = aligned_gpu_address; + writer->buf->cpu_va = writer->buf->cpu_va + alignment_offset; + if (writer->buf->size < alignment_offset) { + writer->status = VPE_STATUS_BUFFER_OVERFLOW; + return; + } + + writer->buf->size -= alignment_offset; + /* Buffer does not have enough space to write */ if (writer->buf->size < sizeof(uint32_t)) { writer->status = VPE_STATUS_BUFFER_OVERFLOW; diff --git a/src/amd/vpelib/src/core/inc/cdc.h b/src/amd/vpelib/src/core/inc/cdc.h index e5cd19fbc74..7f519325228 100644 --- a/src/amd/vpelib/src/core/inc/cdc.h +++ b/src/amd/vpelib/src/core/inc/cdc.h @@ -50,7 +50,8 @@ struct cdc_funcs { void (*program_global_sync)( struct cdc *cdc, uint32_t vupdate_offset, uint32_t vupdate_width, uint32_t vready_offset); - void (*program_p2b_config)(struct cdc *cdc, enum vpe_surface_pixel_format format); + void (*program_p2b_config)(struct cdc *cdc, enum vpe_surface_pixel_format format, + enum vpe_swizzle_mode_values swizzle, const struct vpe_rect *viewport); /** segment specific */ void (*program_viewport)( diff --git a/src/amd/vpelib/src/core/inc/config_writer.h b/src/amd/vpelib/src/core/inc/config_writer.h index c6ee05701d2..a94708ba6be 100644 --- a/src/amd/vpelib/src/core/inc/config_writer.h +++ b/src/amd/vpelib/src/core/inc/config_writer.h @@ -81,6 +81,7 @@ struct config_writer { */ uint64_t base_gpu_va; uint64_t base_cpu_va; + uint16_t gpu_addr_alignment; enum config_type type; bool completed; diff --git a/src/amd/vpelib/src/core/inc/mpc.h b/src/amd/vpelib/src/core/inc/mpc.h index 8e7406b54b2..710d9e096c7 100644 --- a/src/amd/vpelib/src/core/inc/mpc.h +++ b/src/amd/vpelib/src/core/inc/mpc.h @@ -80,8 +80,8 @@ struct mpcc_blnd_cfg { struct vpe_color bg_color; /* background color */ enum mpcc_alpha_blend_mode alpha_mode; /* alpha blend mode */ bool pre_multiplied_alpha; /* alpha pre-multiplied mode flag */ - uint8_t global_gain; - uint8_t global_alpha; + uint16_t global_gain; + uint16_t global_alpha; bool overlap_only; /* MPCC top/bottom gain settings */