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ir3: don't sync every TCS/GEOM block

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TCS/GEOM shaders need (sy)(ss) on their first instruction but we
accidentally set it on the first instruction of every block.

Signed-off-by: Job Noorman <jnoorman@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34257>
This commit is contained in:
Job Noorman
2025-03-28 12:55:11 +01:00
committed by Marge Bot
parent 3ba315f205
commit ee0ee2a317
1 changed files with 4 additions and 6 deletions
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src/freedreno/ir3/ir3_compiler_nir.c
+4 -6
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@@ -5985,12 +5985,10 @@ ir3_compile_shader_nir(struct ir3_compiler *compiler,
* know what we might have to wait on when coming in from VS chsh. * know what we might have to wait on when coming in from VS chsh.
*/ */
if (so->type == MESA_SHADER_TESS_CTRL || so->type == MESA_SHADER_GEOMETRY) { if (so->type == MESA_SHADER_TESS_CTRL || so->type == MESA_SHADER_GEOMETRY) {
foreach_block (block, &ir->block_list) { struct ir3_block *first_block = ir3_start_block(ir);
foreach_instr (instr, &block->instr_list) { struct ir3_instruction *first_instr = list_first_entry(
instr->flags |= IR3_INSTR_SS | IR3_INSTR_SY; &first_block->instr_list, struct ir3_instruction, node);
break; first_instr->flags |= IR3_INSTR_SS | IR3_INSTR_SY;
}
}
} }
if (ctx->compiler->gen >= 7 && so->type == MESA_SHADER_COMPUTE) { if (ctx->compiler->gen >= 7 && so->type == MESA_SHADER_COMPUTE) {