From ec4e5ef0f7aa0463301c71bdf4a9a3b53a18037b Mon Sep 17 00:00:00 2001 From: Ganesh Belgur Ramachandra Date: Sat, 20 Jul 2024 00:26:36 +0530 Subject: [PATCH] amd/common: skip lane size determination for chips without image opcodes (e.g. gfx940) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This fixes VAAPI decode performance issues. Fixes: 5b3e1a05329 ("radeonsi: change the compute blit to clear/blit multiple pixels per lane") Reviewed-by: Marek Olšák Part-of: --- src/amd/common/ac_nir_meta_cs_blit.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/amd/common/ac_nir_meta_cs_blit.c b/src/amd/common/ac_nir_meta_cs_blit.c index 1bdccdf5792..8b2186e16b3 100644 --- a/src/amd/common/ac_nir_meta_cs_blit.c +++ b/src/amd/common/ac_nir_meta_cs_blit.c @@ -679,7 +679,8 @@ ac_prepare_compute_blit(const struct ac_cs_blit_options *options, */ if (blit->dst.surf->bpe <= 8 && (is_resolve ? src_samples : dst_samples) <= 4 && /* Small blits don't benefit. */ - width * height * depth * blit->dst.surf->bpe * dst_samples > 128 * 1024) { + width * height * depth * blit->dst.surf->bpe * dst_samples > 128 * 1024 && + info->has_image_opcodes) { if (is_3d_tiling) { /* Thick tiling. */ if (!is_clear && blit->src.surf->is_linear) {