From ec15cdfa2a3672a881ca798222c8bad3ff12a0aa Mon Sep 17 00:00:00 2001 From: Caio Oliveira Date: Fri, 23 Aug 2024 00:25:42 -0700 Subject: [PATCH] intel/brw: Pack brw_reg struct The alignment required for the second union (has 64-bit size) causes a hole between the first and second union. Move the remaining data there. In 64-bit build, shrinks brw_reg from 24 bytes to 16 bytes. And by consequence, shirnks fs_inst from 200 bytes to 160 bytes, making it use one less cacheline. Reviewed-by: Kenneth Graunke Part-of: --- src/intel/compiler/brw_reg.h | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/src/intel/compiler/brw_reg.h b/src/intel/compiler/brw_reg.h index b744d8808f3..92d9c8ad102 100644 --- a/src/intel/compiler/brw_reg.h +++ b/src/intel/compiler/brw_reg.h @@ -168,6 +168,12 @@ typedef struct brw_reg { uint32_t bits; }; + /** Offset from the start of the virtual register in bytes. */ + uint16_t offset; + + /** Register region horizontal stride of virtual registers */ + uint8_t stride; + union { struct { unsigned nr; @@ -188,12 +194,6 @@ typedef struct brw_reg { unsigned ud; }; - /** Offset from the start of the virtual register in bytes. */ - uint16_t offset; - - /** Register region horizontal stride of virtual registers */ - uint8_t stride; - #ifdef __cplusplus /* TODO: Remove this constructor to make this type a POD. Need * to make sure that rest of compiler doesn't rely on type or