From ebe66dee08e4d76e3498694c9fb7f3693cdd82d0 Mon Sep 17 00:00:00 2001 From: Samuel Pitoiset Date: Tue, 24 Sep 2024 17:54:11 +0200 Subject: [PATCH] radv: move emitting some RT user SGPRs when the RT pipeline is emitted Signed-off-by: Samuel Pitoiset Part-of: --- src/amd/vulkan/radv_cmd_buffer.c | 36 +++++++++++++++++--------------- 1 file changed, 19 insertions(+), 17 deletions(-) diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c index cfa23663a06..97cc277f988 100644 --- a/src/amd/vulkan/radv_cmd_buffer.c +++ b/src/amd/vulkan/radv_cmd_buffer.c @@ -7620,12 +7620,29 @@ radv_emit_compute_pipeline(struct radv_cmd_buffer *cmd_buffer, struct radv_compu if (pipeline == cmd_buffer->state.emitted_compute_pipeline) return; - radeon_check_space(device->ws, cmd_buffer->cs, pdev->info.gfx_level >= GFX10 ? 19 : 16); + radeon_check_space(device->ws, cmd_buffer->cs, pdev->info.gfx_level >= GFX10 ? 25 : 22); if (pipeline->base.type == RADV_PIPELINE_COMPUTE) { radv_emit_compute_shader(pdev, cmd_buffer->cs, cmd_buffer->state.shaders[MESA_SHADER_COMPUTE]); } else { - radv_emit_compute_shader(pdev, cmd_buffer->cs, cmd_buffer->state.rt_prolog); + const struct radv_shader *rt_prolog = cmd_buffer->state.rt_prolog; + + radv_emit_compute_shader(pdev, cmd_buffer->cs, rt_prolog); + + const uint32_t ray_dynamic_callback_stack_base_offset = + radv_get_user_sgpr_loc(rt_prolog, AC_UD_CS_RAY_DYNAMIC_CALLABLE_STACK_BASE); + if (ray_dynamic_callback_stack_base_offset) { + const struct radv_shader_info *cs_info = &rt_prolog->info; + radeon_set_sh_reg(cmd_buffer->cs, ray_dynamic_callback_stack_base_offset, + rt_prolog->config.scratch_bytes_per_wave / cs_info->wave_size); + } + + const uint32_t traversal_shader_addr_offset = radv_get_user_sgpr_loc(rt_prolog, AC_UD_CS_TRAVERSAL_SHADER_ADDR); + struct radv_shader *traversal_shader = cmd_buffer->state.shaders[MESA_SHADER_INTERSECTION]; + if (traversal_shader_addr_offset && traversal_shader) { + uint64_t traversal_va = traversal_shader->va | radv_rt_priority_traversal; + radv_emit_shader_pointer(device, cmd_buffer->cs, traversal_shader_addr_offset, traversal_va, true); + } } cmd_buffer->state.emitted_compute_pipeline = pipeline; @@ -12333,21 +12350,6 @@ radv_trace_rays(struct radv_cmd_buffer *cmd_buffer, VkTraceRaysIndirectCommand2K radv_emit_shader_pointer(device, cmd_buffer->cs, ray_launch_size_addr_offset, launch_size_va, true); } - const uint32_t ray_dynamic_callback_stack_base_offset = - radv_get_user_sgpr_loc(rt_prolog, AC_UD_CS_RAY_DYNAMIC_CALLABLE_STACK_BASE); - if (ray_dynamic_callback_stack_base_offset) { - const struct radv_shader_info *cs_info = &rt_prolog->info; - radeon_set_sh_reg(cmd_buffer->cs, ray_dynamic_callback_stack_base_offset, - rt_prolog->config.scratch_bytes_per_wave / cs_info->wave_size); - } - - const uint32_t traversal_shader_addr_offset = radv_get_user_sgpr_loc(rt_prolog, AC_UD_CS_TRAVERSAL_SHADER_ADDR); - struct radv_shader *traversal_shader = cmd_buffer->state.shaders[MESA_SHADER_INTERSECTION]; - if (traversal_shader_addr_offset && traversal_shader) { - uint64_t traversal_va = traversal_shader->va | radv_rt_priority_traversal; - radv_emit_shader_pointer(device, cmd_buffer->cs, traversal_shader_addr_offset, traversal_va, true); - } - assert(cmd_buffer->cs->cdw <= cdw_max); radv_dispatch(cmd_buffer, &info, pipeline, rt_prolog, VK_PIPELINE_BIND_POINT_RAY_TRACING_KHR);