intel/compiler: Validation for DPAS instructions
v2: s/regiser/register/g in messages. Noticed by Caio. Add more context to the sub-byte precision error message. Suggested by Caio. Reviewed-by: Caio Oliveira <caio.oliveira@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25994>
This commit is contained in:
Ian Romanick
@@ -3136,3 +3136,396 @@ TEST_P(validation_test, add3_immediate_types)
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clear_instructions(p);
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}
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}
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TEST_P(validation_test, dpas_sdepth)
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{
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if (devinfo.verx10 < 125)
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return;
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static const enum gfx12_systolic_depth depth[] = {
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BRW_SYSTOLIC_DEPTH_16,
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BRW_SYSTOLIC_DEPTH_2,
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BRW_SYSTOLIC_DEPTH_4,
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BRW_SYSTOLIC_DEPTH_8,
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};
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for (unsigned i = 0; i < ARRAY_SIZE(depth); i++) {
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brw_DPAS(p,
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depth[i],
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8,
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retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_F),
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null,
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retype(brw_vec8_grf(16, 0), BRW_REGISTER_TYPE_HF),
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retype(brw_vec8_grf(32, 0), BRW_REGISTER_TYPE_HF));
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const bool expected_result = depth[i] == BRW_SYSTOLIC_DEPTH_8;
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EXPECT_EQ(expected_result, validate(p)) <<
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"Encoded systolic depth value is: " << depth[i];
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clear_instructions(p);
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}
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}
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TEST_P(validation_test, dpas_exec_size)
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{
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if (devinfo.verx10 < 125)
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return;
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static const enum brw_execution_size test_vectors[] = {
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BRW_EXECUTE_1,
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BRW_EXECUTE_2,
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BRW_EXECUTE_4,
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BRW_EXECUTE_8,
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BRW_EXECUTE_16,
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BRW_EXECUTE_32,
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};
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for (unsigned i = 0; i < ARRAY_SIZE(test_vectors); i++) {
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brw_set_default_exec_size(p, test_vectors[i]);
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brw_DPAS(p,
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BRW_SYSTOLIC_DEPTH_8,
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8,
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retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_F),
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null,
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retype(brw_vec8_grf(16, 0), BRW_REGISTER_TYPE_HF),
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retype(brw_vec8_grf(32, 0), BRW_REGISTER_TYPE_HF));
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const bool expected_result = test_vectors[i] == BRW_EXECUTE_8;
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EXPECT_EQ(expected_result, validate(p)) <<
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"Exec size = " << (1u << test_vectors[i]);
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clear_instructions(p);
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}
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brw_set_default_exec_size(p, BRW_EXECUTE_8);
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}
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TEST_P(validation_test, dpas_sub_byte_precision)
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{
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if (devinfo.verx10 < 125)
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return;
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static const struct {
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brw_reg_type dst_type;
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brw_reg_type src0_type;
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brw_reg_type src1_type;
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enum gfx12_sub_byte_precision src1_prec;
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brw_reg_type src2_type;
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enum gfx12_sub_byte_precision src2_prec;
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bool expected_result;
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} test_vectors[] = {
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{
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BRW_REGISTER_TYPE_F,
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BRW_REGISTER_TYPE_F,
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BRW_REGISTER_TYPE_HF, BRW_SUB_BYTE_PRECISION_NONE,
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BRW_REGISTER_TYPE_HF, BRW_SUB_BYTE_PRECISION_NONE,
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true,
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},
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{
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BRW_REGISTER_TYPE_F,
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BRW_REGISTER_TYPE_F,
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BRW_REGISTER_TYPE_HF, BRW_SUB_BYTE_PRECISION_NONE,
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BRW_REGISTER_TYPE_HF, BRW_SUB_BYTE_PRECISION_4BIT,
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false,
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},
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{
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BRW_REGISTER_TYPE_F,
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BRW_REGISTER_TYPE_F,
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BRW_REGISTER_TYPE_HF, BRW_SUB_BYTE_PRECISION_NONE,
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BRW_REGISTER_TYPE_HF, BRW_SUB_BYTE_PRECISION_2BIT,
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false,
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},
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{
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BRW_REGISTER_TYPE_F,
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BRW_REGISTER_TYPE_F,
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BRW_REGISTER_TYPE_HF, BRW_SUB_BYTE_PRECISION_4BIT,
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BRW_REGISTER_TYPE_HF, BRW_SUB_BYTE_PRECISION_NONE,
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false,
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},
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{
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BRW_REGISTER_TYPE_F,
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BRW_REGISTER_TYPE_F,
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BRW_REGISTER_TYPE_HF, BRW_SUB_BYTE_PRECISION_2BIT,
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BRW_REGISTER_TYPE_HF, BRW_SUB_BYTE_PRECISION_NONE,
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false,
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},
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{
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BRW_REGISTER_TYPE_UD,
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BRW_REGISTER_TYPE_UD,
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BRW_REGISTER_TYPE_UB, BRW_SUB_BYTE_PRECISION_NONE,
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BRW_REGISTER_TYPE_UB, BRW_SUB_BYTE_PRECISION_NONE,
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true,
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},
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{
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BRW_REGISTER_TYPE_UD,
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BRW_REGISTER_TYPE_UD,
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BRW_REGISTER_TYPE_UB, BRW_SUB_BYTE_PRECISION_NONE,
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BRW_REGISTER_TYPE_UB, BRW_SUB_BYTE_PRECISION_4BIT,
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true,
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},
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{
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BRW_REGISTER_TYPE_UD,
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BRW_REGISTER_TYPE_UD,
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BRW_REGISTER_TYPE_UB, BRW_SUB_BYTE_PRECISION_NONE,
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BRW_REGISTER_TYPE_UB, BRW_SUB_BYTE_PRECISION_2BIT,
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true,
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},
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{
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BRW_REGISTER_TYPE_UD,
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BRW_REGISTER_TYPE_UD,
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BRW_REGISTER_TYPE_UB, BRW_SUB_BYTE_PRECISION_NONE,
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BRW_REGISTER_TYPE_UB, (enum gfx12_sub_byte_precision) 3,
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false,
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},
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{
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BRW_REGISTER_TYPE_UD,
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BRW_REGISTER_TYPE_UD,
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BRW_REGISTER_TYPE_UB, BRW_SUB_BYTE_PRECISION_4BIT,
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BRW_REGISTER_TYPE_UB, BRW_SUB_BYTE_PRECISION_NONE,
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true,
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},
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{
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BRW_REGISTER_TYPE_UD,
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BRW_REGISTER_TYPE_UD,
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BRW_REGISTER_TYPE_UB, BRW_SUB_BYTE_PRECISION_2BIT,
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BRW_REGISTER_TYPE_UB, BRW_SUB_BYTE_PRECISION_NONE,
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true,
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},
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{
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BRW_REGISTER_TYPE_UD,
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BRW_REGISTER_TYPE_UD,
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BRW_REGISTER_TYPE_UB, (enum gfx12_sub_byte_precision) 3,
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BRW_REGISTER_TYPE_UB, BRW_SUB_BYTE_PRECISION_NONE,
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false,
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},
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};
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for (unsigned i = 0; i < ARRAY_SIZE(test_vectors); i++) {
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brw_inst *inst =
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brw_DPAS(p,
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BRW_SYSTOLIC_DEPTH_8,
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8,
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retype(brw_vec8_grf(0, 0), test_vectors[i].dst_type),
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retype(brw_vec8_grf(16, 0), test_vectors[i].src0_type),
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retype(brw_vec8_grf(32, 0), test_vectors[i].src1_type),
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retype(brw_vec8_grf(48, 0), test_vectors[i].src2_type));
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brw_inst_set_dpas_3src_src1_subbyte(&devinfo, inst,
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test_vectors[i].src1_prec);
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brw_inst_set_dpas_3src_src2_subbyte(&devinfo, inst,
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test_vectors[i].src2_prec);
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EXPECT_EQ(test_vectors[i].expected_result, validate(p)) <<
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"test vector index = " << i;
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clear_instructions(p);
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}
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}
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TEST_P(validation_test, dpas_types)
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{
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if (devinfo.verx10 < 125)
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return;
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#define TV(a, b, c, d, r) \
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{ BRW_REGISTER_TYPE_ ## a, BRW_REGISTER_TYPE_ ## b, \
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BRW_REGISTER_TYPE_ ## c, BRW_REGISTER_TYPE_ ## d, \
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r }
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static const struct {
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brw_reg_type dst_type;
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brw_reg_type src0_type;
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brw_reg_type src1_type;
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brw_reg_type src2_type;
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bool expected_result;
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} test_vectors[] = {
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TV( F, F, HF, HF, true),
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TV( F, HF, HF, HF, false),
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TV(HF, F, HF, HF, false),
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TV( F, F, F, HF, false),
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TV( F, F, HF, F, false),
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TV(DF, DF, DF, DF, false),
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TV(DF, DF, DF, F, false),
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TV(DF, DF, F, DF, false),
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TV(DF, F, DF, DF, false),
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TV(DF, DF, DF, HF, false),
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TV(DF, DF, HF, DF, false),
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TV(DF, HF, DF, DF, false),
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TV(UD, UD, UB, UB, true),
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TV(UD, UD, UB, UD, false),
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TV(UD, UD, UD, UB, false),
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TV(UD, UD, UB, UW, false),
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TV(UD, UD, UW, UB, false),
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TV(UD, UB, UB, UB, false),
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TV(UD, UW, UB, UB, false),
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TV(UQ, UQ, UB, UB, false),
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TV(UQ, UQ, UB, UQ, false),
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TV(UQ, UQ, UQ, UB, false),
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TV(UQ, UQ, UB, UW, false),
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TV(UQ, UQ, UW, UB, false),
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TV( D, D, B, B, true),
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TV( D, D, B, UB, true),
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TV( D, D, UB, B, true),
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TV( D, UD, B, B, true),
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TV( D, D, B, D, false),
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TV( D, D, D, B, false),
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TV( D, D, B, W, false),
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TV( D, D, W, B, false),
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TV( D, B, B, B, false),
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TV( D, W, B, B, false),
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TV( Q, Q, B, B, false),
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TV( Q, Q, B, Q, false),
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TV( Q, Q, Q, B, false),
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TV( Q, Q, B, W, false),
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TV( Q, Q, W, B, false),
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TV(UD, UD, UB, B, false),
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TV(UD, UD, B, UB, false),
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TV(UD, D, UB, UB, false),
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};
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#undef TV
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for (unsigned i = 0; i < ARRAY_SIZE(test_vectors); i++) {
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brw_DPAS(p,
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BRW_SYSTOLIC_DEPTH_8,
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8,
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retype(brw_vec8_grf(0, 0), test_vectors[i].dst_type),
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retype(brw_vec8_grf(16, 0), test_vectors[i].src0_type),
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retype(brw_vec8_grf(32, 0), test_vectors[i].src1_type),
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retype(brw_vec8_grf(48, 0), test_vectors[i].src2_type));
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EXPECT_EQ(test_vectors[i].expected_result, validate(p)) <<
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"test vector index = " << i;
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clear_instructions(p);
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}
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}
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TEST_P(validation_test, dpas_src_subreg_nr)
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{
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if (devinfo.verx10 < 125)
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return;
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#define TV(dt, od, t0, o0, t1, o1, o2, r) { \
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BRW_REGISTER_TYPE_ ## dt, od, \
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BRW_REGISTER_TYPE_ ## t0, o0, \
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BRW_REGISTER_TYPE_ ## t1, o1, o2, \
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r }
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static const struct {
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brw_reg_type dst_type;
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unsigned dst_subnr;
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brw_reg_type src0_type;
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unsigned src0_subnr;
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brw_reg_type src1_src2_type;
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unsigned src1_subnr;
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unsigned src2_subnr;
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bool expected_result;
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} test_vectors[] = {
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TV( F, 0, F, 0, HF, 0, 0, true),
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TV( D, 0, D, 0, B, 0, 0, true),
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TV( D, 0, D, 0, UB, 0, 0, true),
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TV( D, 0, UD, 0, B, 0, 0, true),
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TV( F, 1, F, 0, HF, 0, 0, false),
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TV( F, 2, F, 0, HF, 0, 0, false),
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TV( F, 3, F, 0, HF, 0, 0, false),
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TV( F, 4, F, 0, HF, 0, 0, false),
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TV( F, 5, F, 0, HF, 0, 0, false),
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TV( F, 6, F, 0, HF, 0, 0, false),
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TV( F, 7, F, 0, HF, 0, 0, false),
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TV( F, 0, F, 1, HF, 0, 0, false),
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TV( F, 0, F, 2, HF, 0, 0, false),
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TV( F, 0, F, 3, HF, 0, 0, false),
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TV( F, 0, F, 4, HF, 0, 0, false),
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TV( F, 0, F, 5, HF, 0, 0, false),
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TV( F, 0, F, 6, HF, 0, 0, false),
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TV( F, 0, F, 7, HF, 0, 0, false),
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TV( F, 0, F, 0, HF, 1, 0, false),
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TV( F, 0, F, 0, HF, 2, 0, false),
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TV( F, 0, F, 0, HF, 3, 0, false),
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TV( F, 0, F, 0, HF, 4, 0, false),
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TV( F, 0, F, 0, HF, 5, 0, false),
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TV( F, 0, F, 0, HF, 6, 0, false),
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TV( F, 0, F, 0, HF, 7, 0, false),
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TV( F, 0, F, 0, HF, 8, 0, false),
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TV( F, 0, F, 0, HF, 9, 0, false),
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TV( F, 0, F, 0, HF, 10, 0, false),
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TV( F, 0, F, 0, HF, 11, 0, false),
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TV( F, 0, F, 0, HF, 12, 0, false),
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TV( F, 0, F, 0, HF, 13, 0, false),
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TV( F, 0, F, 0, HF, 14, 0, false),
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TV( F, 0, F, 0, HF, 15, 0, false),
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TV( F, 0, F, 0, HF, 0, 1, false),
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TV( F, 0, F, 0, HF, 0, 2, false),
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TV( F, 0, F, 0, HF, 0, 3, false),
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TV( F, 0, F, 0, HF, 0, 4, false),
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TV( F, 0, F, 0, HF, 0, 5, false),
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TV( F, 0, F, 0, HF, 0, 6, false),
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TV( F, 0, F, 0, HF, 0, 7, false),
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TV( F, 0, F, 0, HF, 0, 8, false),
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TV( F, 0, F, 0, HF, 0, 9, false),
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TV( F, 0, F, 0, HF, 0, 10, false),
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TV( F, 0, F, 0, HF, 0, 11, false),
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TV( F, 0, F, 0, HF, 0, 12, false),
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TV( F, 0, F, 0, HF, 0, 13, false),
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TV( F, 0, F, 0, HF, 0, 14, false),
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TV( F, 0, F, 0, HF, 0, 15, false),
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/* These meet the requirements, but they specify a subnr that is part of
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* the next register. It is currently not possible to specify a subnr of
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* 32 for the B and UB values because brw_reg::subnr is only 5 bits.
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*/
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TV( F, 16, F, 0, HF, 0, 0, false),
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TV( F, 0, F, 16, HF, 0, 0, false),
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TV( F, 0, F, 0, HF, 0, 16, false),
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TV( D, 16, D, 0, B, 0, 0, false),
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TV( D, 0, D, 16, B, 0, 0, false),
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};
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#undef TV
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for (unsigned i = 0; i < ARRAY_SIZE(test_vectors); i++) {
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struct brw_reg dst =
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retype(brw_vec8_grf( 0, 0), test_vectors[i].dst_type);
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struct brw_reg src0 =
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retype(brw_vec8_grf(16, 0), test_vectors[i].src0_type);
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struct brw_reg src1 =
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retype(brw_vec8_grf(32, 0), test_vectors[i].src1_src2_type);
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struct brw_reg src2 =
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retype(brw_vec8_grf(48, 0), test_vectors[i].src1_src2_type);
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/* subnr for DPAS is in units of datatype precision instead of bytes as
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* it is for every other instruction. Set the value by hand instead of
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* using byte_offset() or similar.
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*/
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dst.subnr = test_vectors[i].dst_subnr;
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src0.subnr = test_vectors[i].src0_subnr;
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src1.subnr = test_vectors[i].src1_subnr;
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src2.subnr = test_vectors[i].src2_subnr;
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brw_DPAS(p, BRW_SYSTOLIC_DEPTH_8, 8, dst, src0, src1, src2);
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EXPECT_EQ(test_vectors[i].expected_result, validate(p)) <<
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"test vector index = " << i;
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clear_instructions(p);
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}
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}
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