diff --git a/src/amd/common/ac_gpu_info.c b/src/amd/common/ac_gpu_info.c
index 1f1d5550efb..7e45ae20e86 100644
--- a/src/amd/common/ac_gpu_info.c
+++ b/src/amd/common/ac_gpu_info.c
@@ -2472,10 +2472,9 @@ void ac_get_hs_info(const struct radeon_info *info,
                              S_0089B0_OFFCHIP_GRANULARITY(wg_size_enum);
    }
 
-   hs->tess_factor_ring_size = 48 * 1024 * info->max_se;
-   hs->tess_offchip_ring_offset = align(hs->tess_factor_ring_size, 64 * 1024);
    hs->tess_offchip_ring_size = num_workgroups * wg_size_in_dwords * 4;
-   hs->total_tess_ring_size = hs->tess_offchip_ring_offset + hs->tess_offchip_ring_size;
+   hs->tess_factor_ring_size = 48 * 1024 * info->max_se;
+   hs->total_tess_ring_size = hs->tess_offchip_ring_size + hs->tess_factor_ring_size;
 }
 
 static uint16_t get_task_num_entries(enum radeon_family fam)
diff --git a/src/amd/common/ac_gpu_info.h b/src/amd/common/ac_gpu_info.h
index 7f1a7b0ab93..933e235ec06 100644
--- a/src/amd/common/ac_gpu_info.h
+++ b/src/amd/common/ac_gpu_info.h
@@ -350,7 +350,6 @@ unsigned ac_get_compute_resource_limits(const struct radeon_info *info,
 struct ac_hs_info {
    uint32_t hs_offchip_param;
    uint32_t tess_factor_ring_size;
-   uint32_t tess_offchip_ring_offset;
    uint32_t tess_offchip_ring_size;
    uint32_t total_tess_ring_size;
 };
diff --git a/src/amd/vulkan/radv_queue.c b/src/amd/vulkan/radv_queue.c
index 59ad91c801c..c9b897f2df6 100644
--- a/src/amd/vulkan/radv_queue.c
+++ b/src/amd/vulkan/radv_queue.c
@@ -313,10 +313,10 @@ radv_fill_shader_rings(struct radv_device *device, uint32_t *desc, struct radeon
    desc += 8;
 
    if (tess_rings_bo) {
-      radv_set_ring_buffer(pdev, tess_rings_bo, 0, pdev->hs.tess_factor_ring_size, false, false, true, 0, 0, &desc[0]);
+      radv_set_ring_buffer(pdev, tess_rings_bo, pdev->hs.tess_offchip_ring_size, pdev->hs.tess_factor_ring_size, false,
+                           false, true, 0, 0, &desc[0]);
 
-      radv_set_ring_buffer(pdev, tess_rings_bo, pdev->hs.tess_offchip_ring_offset, pdev->hs.tess_offchip_ring_size,
-                           false, false, true, 0, 0, &desc[4]);
+      radv_set_ring_buffer(pdev, tess_rings_bo, 0, pdev->hs.tess_offchip_ring_size, false, false, true, 0, 0, &desc[4]);
    }
 
    desc += 8;
@@ -398,7 +398,7 @@ radv_emit_tess_factor_ring(struct radv_device *device, struct radeon_cmdbuf *cs,
       return;
 
    tf_ring_size = pdev->hs.tess_factor_ring_size / 4;
-   tf_va = radv_buffer_get_va(tess_rings_bo);
+   tf_va = radv_buffer_get_va(tess_rings_bo) + pdev->hs.tess_offchip_ring_size;
 
    radv_cs_add_buffer(device->ws, cs, tess_rings_bo);